MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 189

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7
7.2.9 Synchronous Operation with DSACKx
7-28
Although cycles terminated with the DSACKx signals are classified as asyn-
is completely ignored.
chronous and cycles terminated with STERM are classified as synchronous,
cycles terminated with DSACKx can also operate synchronously in that sig-
The devices that use these cycles must synchronize the responses to the
For asynchronous read cycles, the value of CIIN is internally latched on the
rising edge of bus cycle state 4. Refer to 7.3.1 Asynchronous Read Cycle for
more details on the states for asynchonous read cycles.
During any bus cycle terminated by DSACKx or BERR, the assertion of CBACK
nals are interpreted relative to clock edges.
MC68030 clock to be synchronous. Since they terminate bus cycles with the
DSACKx signals, the dynamic bus sizing capabilities of the MC68030 are
available. In addition, the minimum cycle time for these cycles is also three
clocks.
To support those systems that use the system clock to generate DSACKx and
other asynchronous inputs, the asynchronous input setup time (parameter
the setup and hold times are met for the assertion or negation of a signal,
#47A) and the asynchronous input hold time (parameter #47B) are given. If
such as DSACKx, the processor can be guaranteed to recognize that signal
falling edge of $2 and obeys the proper bus protocol by maintaining DSACKx
level on that specific falling edge of the system clock. If the assertion of
DSACKx is recognized on a particular falling edge of the clock, valid data is
latched into the processor (for a read cycle) on the next falling clock edge
provided the data meets the data setup time (parameter #27). In this case,
parameter #31 for asynchronous operation can be ignored. The timing pa-
rameters referred to are described in MC68030EC/D, MC68030 Electrical Spec-
ifications. If a system asserts DSACKx for the required window around the
(and/or BERR/HALT) until and throughout the clock edge that negates AS
(with the appropriate asynchronous input hold time specifiedby parameter
#47B), no wait states are inserted. The bus cycle runs at its maximum speed
(three clocks per cycle) for bus cycles terminated with DSACKx.
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