MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 493

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

1
11.6.2
11-30
11.6.3 Calculate Effective A d d r e s s (cea)
I
The calculate effective address table indicates the number of clock periods
time is only included for the first level of indirection on memory indirect
All timing data assumes two-clock reads and writes.
addressing modes. The effective addresses are divided by their formats (refer
to 2.5 Effective Address Encoding Summary). For instruction-cache case and
for no-cache case, the total number of clock cycles is outside the
The number of read, prefetch, and write cycles is given inside the parentheses
needed for the processor to calculate the specified effective address. Fetch
as (r/p/w). The read, prefetch, and write cycles are included in the total clock
cycle number.
FULL FORMAT EXTENSION WORD(S) (CONTINUED)
NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing.
%= Total head for fetch immediate effective address timing includes the head time for the operation.
Fetch I m m e d i a t e Effective A d d r e s s ( f l e a ) ( C o n t i n u e d )
B= Base Address: 0, Anl PC, Xn, An+Xn, PC+Xn. Form does not affect timing.
#(data).L,([d 16'Bj,d16)
#(data).W,([d16,B],l,d 16)
# ( data).L,([d16,B],l,d16)
#(data).W,([d16,B],d32)
#(data).L,([d 16,B],d32)
#(data).W,(!d16,B],l,d32)
#(data).L,([di 6,B],l,d32)
#(data).W,([d32,B])
#(data).L,([d32,B])
#(d ata).W,([d32,B],l)
#(data).L,([d32,B],l)
#(data).W,( [d32,B],d 16)
#(data).L,([d32,B],d16)
#(data).W,([d32,B],l,d 16)
#(data).L,([d32,B],l,d 16)
#(data).W,([d32,B],d32)
#(data).L,([d32,B],d32)
#(data~.W,([d32,B],l,d32)
#(data).L,([d32,B],l,d32)
I= Index: 0, Xn
#(data).W,([d16,B], d 16)
Address Mode
M C 6 8 0 3 0 U S E R ' S M A N U A L
I
Head
8
6
8
6
8
6
8
8
6
6
8
6
8
6
8
6
6
8
6
8
I
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Tail
I I-Cache Case INo-Cache Case I
18(2/0/0)
16(2/0/0)
18(2/0/0)
18(2/0/0)
20(2/0/0)
20(2/0/0)
20(2/0/0)
22(2/0/0)
20(2/0/0)
22(2/0/0)
20(2/0/0)
22(2/0/0)
20(2/O/O)
22(2/0/0)
16(2/0/0)
16(2/0/0)
18(2/0/0)
16(2/0/0)
18(2/0/0)
18(2/0/0)
parentheses.
M O T O R O L A
20(2/3/0)
21(2/3/0)
23(2/3/0)
20(2/3/0)
21(2/3/0)
22(2/3/0)
24(2/3/0)
23(2/3/0)
18(2/2/0)
18(2/2/0)
19(2/3/0)
21(2/3/0)
19(2/3/0)
19(2/2/0)
19(2/2/0)
21(2/3/0)
22(2/3/0)
24(2/3/0)
25(2/4/0)
25(2/4/0)