MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 549

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

12
12.5.2 A 2-1-1-1 Burst Mode Memory Bank Using SRAMs
12-24
The MC68030 normally attains its lowest bus utilization when the external
to this can occur. For instance, when a large amount of memory accesses
The system must also provide any STERM or CBACK consolidation circuitry
or ports). In Figure 12-14, this consolidation circuitry is shown as an AND
gate.
The memory bank can be divided into four sections:
The first section is completely contained within the PAL16L8D. The PAL equa-
tions are the same as those provided in Figure 12-8 for the two-clock read,
three-clock write memory bank, although slightly modified to support the
with the addition of a flip-flop to delay the TERM signal by one clock. The
with three-clock bus cycles.
memory system can support a 2-1-1-1 burst protocol. However, exceptions
are not governed by the locality of reference principles, burst accesses may
ory bank with 256K bytes that can operate with a 20-MHz MC68030. Nonburst
reads and all write cycles execute in two clocks.
Figure 12-14 shows the complete memory bank and its connection to the
as required (e.g., due to the presence of multiple synchronous memory banks
memory (55 ns if < 15.8 MHz). If 20 MHz is still the frequency of choice, the
designer may choose to run three-clock bus cycles. This can be accomplished
resulting memory access time is over 85 ns with a 20-MHz processor running
not decrease bus utilization. This section describes a complete 2-1-1-1 mem-
MC68030. The required parts include:
(2)
(4)
(1)
(1)
2. The burst address generator (provided by the counters).
3. The actual memory section (SRAMs).
4. The buffer section (address and data).
(32)
(4)
(2)
1. The byte select and address decode section (provided by the PAL).
64K x 1 SRAMs 25 ns access time (Motorola's MCM6287-25 or equiv-
74ALS244 buffers
74AS373 latches
74F32 OR gates
74F191 counters
74F04 inverter
PAL16L8D (or equivalent)
alent)
MC68030 USER'S MANUAL
MOTOROLA