MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 174

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.2.2 Misaligned Operands
MOTOROLA
terminates
follows the pattern corresponding to this configuration of the size and address
word portion of the bus (D16-D31). The bus cycle transfers the remaining
timing.
SIZ0_SIZI_A0_A1 =1010 to transfer the remaining 16 bits. SIZ0 and SIZ1
word
signals and places the two least significant bytes of the long word on the
signals for this operation.
example, this example requires two bus cycles. Each bus cycle transfers a
single byte. The size signals for the first cycle specify two bytes; for the
second cycle, one byte. Figure 7-8 shows the associated bus transfer signal
Since operands may reside at any byte boundaries, they may be misaligned.
A byte operand is properly aligned at any address; a word operand is mis-
exceptions if word or long-word operand transfers are attempted at odd-byte
addresses. Although the MC68030 does not enforce any alignment restric-
tions for data operands (including PC relative data addresses), some per-
formance degradation occurs when additional bus cycles are required for
indicate that a word remains to be transferred; A0 and A1 indicate that the
bytes to the word-size port. Figure 7-6 shows the timing of the bus transfer
Figure 7-7 shows a word transfer to an 8-bit bus port. Like the preceding
aligned at an odd address; a long word is misaligned at an address that is
not evenly divisible by four. The MC68000, MC68008, and MC68010 imple-
mentations allow long-word transfers on odd-word boundaries but force
corresponds
031 DATA SUS D24
I
I
15
BYTE MEMORY
Figure 7-7. Example of Word Transfer to Byte Port
the bus cycle.
DP2
WORD DPERAND
to an offset of two from the base address. The multiplexer
I
]
MC68030 USER'S MANUAL
DP3
0
1
It then starts a new bus cycle with
SIZ1
0
I
SIZO
MC68030
0
I
A1
0
O
AO
0
I
OSACK1
MEMORYCONTROL
H
H
OSACKO
L
L
7-13
7