MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 134

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

5.9.3 Bus Grant Acknowledge (BGACK)
5.9.2 Bus Grant (BG)
5.10
5.10.1 Reset (RESET)
5.10.2 Halt (HALT)
5.10,3 Bus Error (BERR)
MOTOROLA
BUS EXCEPTION C O N T R O L S I G N A L S
This output indicates that the MC68030 will release ownership of the bus
Grant
This input indicates that an external device has become the bus master. Refer
to 7.7.3
The following signals are the bus exception control signals for the MC68030.
This bidirectional open-drain signa is used to initiate a system reset. An
external reset signal resets the MC68030 as well as all external devices. A
8.1.1
The halt signal indicates that the processor should suspend bus activity or,
when used with BERR, that the processor should retry the current cycle. Refer
to 7.5 BUS EXCEPTION CONTROL CYCLES for a description of the effects of
The bus error signal indicates that an invalid bus operation is being attempted
master when the current processor bus cycle completes. Refer to 7,7.2
reset signal from the processor (asserted as part of the RESET instruction)
resets external devices only; the internal state of the processor is not altered.
Refer to 7.8 RESET OPERATION for a description of reset bus operation and
HALT on bus operations.
or, when used with HALT, that the processor should retry the current cycle.
effects of BERR on bus operations.
Refer to 7.5 BUS EXCEPTION CONTROL CYCLES for a description of the
Reset Exception
for more information.
Bus Grant Acknowledge
for information about the reset exception.
MC68030 USER'S MANUAL
for more information.
Bus
5-9
5