MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 154

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

XFIRST ACCESS OF 8URST OPERATI O N V
MOTOROLA
BURST MODE REQUESTED AND
REQUI R ED OPERAND OR PREFETCH / ~
four long words in the cache line can be filled in a single burst operation,
The bursting mechanism allows addresses to wrap around so that the entire
structure of the external memory system, address bits A2 and A3 may have
to be incremented externally to select the long words in the proper order for
for the duration of the burst cycle. Figure 6-12 shows an example of this
$6. Because the responding device returns CBACK and STERM (signaling a
the initial address is $06 when CBREQ is asserted, the next entry to be burst
regardless of the initial address and operand alignment. Depending on the
address wraparound. The initial cycle is a long-word access from address
32-bit port), the entire long word at base address $04 is transferred. Since
filled into the cache should correspond to address $08, then $0C, and last,
$00. This addressing is compatible with existing nibble-mode dynamic RAMs,
and can be supported by page and static column modes with an external
loading into the cache. The MC68030 holds the entire address bus constant
modulo 4 counter for A2 and A3.
ACKNOWLEDGED
CYCLE 1
Figure 6-11. Burst Operation Cycles and Burst Mode
Figure 6-12. Burst Filling Wraparound Example
~
BURST MODE BEGINS HERE
i
8URST FILL CYCLE
FINAL CACHE ENTRY
$00
TO BE FILLED
CYCLE 2
MC68030 USER'S MANUAL
I
BURST OPERATI O N
I
X
DPERAND REQUIRED
$04
ACCESS- INCLUDES
FIRST LONG WORD
~
FIRST PART OF
1
BURST FILL CYCLE
CYCLE 3
I
SECOND CACHE ENTRY
$08
i
TO BE FILLED
I
X
J
BURST FILL CYCLE
I
THIRD CACHE ENTRY
$0C
CYCLE 4
TO BE FILLED
I
I
6-17
X
6