MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 116

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

3.5.3 Bit Field Operations
MOTOROLA
The instruction set includes eight instructions that have bit field operands.
The i n s e r t b i t field (BFINS) instruction inserts a bit field stored in a register
field into the least significant bits of a register and extends the sign to the
The set bit field (BFSET) instruction sets all the bits of a field to ones. The
find first one in bit field (BFFFO) instruction scans a bit field from bit 0 to the
An important application of bit field instructions is the manipulation of the
tions can also be used.
to insert or extract bit fields of a register without affecting other fields within
One data type provided by the MC68030 is the bit field, consisting of as many
as 32 consecutive bits. A bit field is defined by an offset from an effective
address and a width value. The offset is a value in the range of -231 through
231 - 1 from the most significant bit (bit 7) at the effective address. The width
is a positive number, 1-32. The most significant bit of a bit field is bit 0; the
bits number in a direction opposite to the bits of an integer.
into a bit field. The extract bit field signed (BFEXTS) instruction loads a bit
left, filling the register. The extract bit field unsigned (BFEXTU) also loads a
bit field, but zero fills the unused portion of the destination register.
clear bit field (BFCLR) instruction clears a field. The change bit field (BFCHG)
instruction complements all the bits in a bit field. These three instructions
all test the previous value of the bit field, setting the condition codes ac-
cordingly. The test bit field (BFTST) instruction tests the value in the field,
setting the condition codes appropriately without altering the bit field. The
into the specified data register. If no bits in the field are set, the field offset
and the field width is loaded into the register.
exponent field in a floating-point number. In the IEEE standard format, the
at the next most significant bit position; the exponent field does not begin
on a byte boundary. The extract bit field (BFEXTU) instruction and the BFTST
setting, and inserting of bit fields in the control registers of the peripherals,
which is another application for bit field instructions. However, control reg-
the register.
right until it finds a bit set to one and loads the bit offset of the first set bit
most significant bit is the sign bit of the mantissa. The exponent value begins
instruction are the most useful for this application, but other bit field instruc-
Programming of input and output operations to peripherals requires testing,
ister locations are not memory locations; therefore, it is not always possible
MC68030 USER'S MANUAL
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