N25Q128A11B1240E NUMONYX, N25Q128A11B1240E Datasheet - Page 167

• Manufacturer Part Number: N25Q128A11B1240E
• Manufacturer: NUMONYX

Specifications of N25Q128A11B1240E

• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 7ns
• Interface Type: Serial (SPI)
• Boot Type: Bottom
• Address Bus: 1b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: TBGA
• Program/erase Volt (typ): 1.7 to 2/8.5 to 9.5V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 8b
• Number Of Words: 16M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / Rohs Status: Supplier Unconfirmed

11
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on VCC) until VCC reaches the correct value:
A safe configuration is provided in
To avoid data corruption and inadvertent write operations during power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the Power On Reset (POR) threshold voltage, VWI - all operations are disabled, and
the device does not respond to any instruction.
Moreover, the device ignores the Write Enable (WREN) instruction and all the modify
instructions until a time delay of tPUW has elapsed after the moment that VCC rises above
the VWI threshold. However, the correct operation of the device is not guaranteed if, by this
time, VCC is still below VCC(min). No Write Status Register, Program or Erase instructions
should be sent until the later of:
These values are specified in
If the time, tVSL, has elapsed, after VCC rises above VCC(min), the device can be selected
for READ instructions even if the tPUW delay has not yet fully elapsed.
After power-up, the device is in the following state:
Normal precautions must be taken for supply line decoupling, to stabilize the VCC supply.
Each device in a system should have the VCC line decoupled by a suitable capacitor close
to the package pins (generally, this capacitor is of the order of 100 nF).
At power-down, when VCC drops from the operating voltage, to below the Power On Reset
(POR) threshold voltage, VWI, all operations are disabled and the device does not respond
to any instruction (the designer needs to be aware that if power-down occurs while a Write,
Program or Erase cycle is in progress, some data corruption may result).
VPPH must be applied only when VCC is stable and in the VCC(min) to VCC(max) voltage
range.
VCC(min) at power-up, and then for a further delay of tVSL
VSS at power-down
tPUW after VCC has passed the VWI threshold
tVSL after VCC has passed the VCC(min) level
The device is in the Standby Power mode (not the Deep Power-down mode)
The Write Enable Latch (WEL) bit is reset
The Write In Progress (WIP) bit is reset
The Lock Registers are configured as: (Write Lock bit, Lock Down bit) = (0,0).
Table 27.: Power-up timing and VWI
Section 3: SPI
Modes.
threshold.
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