N25Q128A11B1240E NUMONYX, N25Q128A11B1240E Datasheet - Page 112

• Manufacturer Part Number: N25Q128A11B1240E
• Manufacturer: NUMONYX

Specifications of N25Q128A11B1240E

• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 7ns
• Interface Type: Serial (SPI)
• Boot Type: Bottom
• Address Bus: 1b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: TBGA
• Program/erase Volt (typ): 1.7 to 2/8.5 to 9.5V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 8b
• Number Of Words: 16M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / Rohs Status: Supplier Unconfirmed

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S
C
DQ0
The Deep Power-down mode automatically stops at power-down, and the device always
powers up in the Standby Power mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for
the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of t
to I
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 42. Deep Power-down instruction sequence
Release from Deep Power-down (RDP)
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down (RDP) instruction. Executing this instruction
takes the device out of the Deep Power-down mode.
The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S)
Low, followed by the instruction code on Serial Data input (DQ0). Chip Select (S) must be
driven Low for the entire duration of the sequence.
The instruction sequence is shown in
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select
(S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven
Low, cause the instruction to be rejected, and not executed.
After Chip Select (S) has been driven High, followed by a delay, t
Standby mode. Chip Select (S) must remain High at least until this period is over. The
device waits to be selected, so that it can receive, decode and execute instructions.
Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write
cycle is in progress, is rejected without having any effects on the cycle that is in progress.
CC2
and the Deep Power-down mode is entered.
0
1
2
Instruction
3
4
5
6
7
Figure
Figure
42.
43.
t
Standby mode
DP
DP
before the supply current is reduced
RDP
Deep power-down mode
, the device is put in the
AI13744