N25Q128A11B1240E NUMONYX, N25Q128A11B1240E Datasheet - Page 161

• Manufacturer Part Number: N25Q128A11B1240E
• Manufacturer: NUMONYX

Specifications of N25Q128A11B1240E

• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 7ns
• Interface Type: Serial (SPI)
• Boot Type: Bottom
• Address Bus: 1b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: TBGA
• Program/erase Volt (typ): 1.7 to 2/8.5 to 9.5V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 8b
• Number Of Words: 16M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / Rohs Status: Supplier Unconfirmed

10
Note:
XIP Operations
XIP (eXecution in Place) mode is available in each protocol: Extended SPI, DIO-SPI, and
QIO-SPI. XIP mode allows the memory to be read simply by sending an address to the
device and then receiving the data on one, two, or four pins in parallel, depending on the
customer requirements. It offers maximum flexibility to the application, saves instruction
overhead, and allows a dramatic reduction to the Random Access time.
You can enable XIP mode in two ways:
Setting to 0 the bit 3 of the Volatile Configuration Register the device is ready to enter in XIP
mode right after the next fast read instruction (by 1, 2 or 4 pin).
While acting on the Non Volatile Configuration Register (bit 11 to bit 9, depending on which
XIP type is required, single, dual or quad I/O) the memory enters in the selected XIP mode
only after the next power-on sequence. The Non Volatile Configuration Register XIP
configuration bits allows the memory to start directly in the required XIP mode (Single, Dual
or Quad) after the power on.
The XIP mode status must be confirmed forcing the XIP confirmation bit to "0", the XIP
confirmation bit is the value on the DQ0 pin during the first dummy clock cycle after the
address in XIP reading instruction. Forcing the bit "1" on DQ0 during the first dummy clock
cycle after the address (XIP Confirmation bit) the memory returns in the previous standard
read mode, that means it will codify as an instruction code the next byte received on the
input pin(s) after the next chip select. Instead, if the XIP mode is confirmed (by forcing the
XIP confirmation bit to 0), after the device next de-selection and selection cycle, the memory
codify the first 3 bytes received on the inputs pin(s) as a new address.
Besides not confirming the XIP mode during the first dummy clock cycle, it is possible to exit
the XIP mode by mean of a dedicated rescue sequence.
For devices with a feature set digit equal to 2 or 4 in the part number (Basic XiP), it is not
necessary to set the Volatile Configuration Register bit 3 to enter XIP mode: it is possible to
enter XIP mode directly by setting XIP Confirmation bit to 1 during the first dummy clock
cycle after a fast read instruction.See
Using the Volatile Configuration Register: this is dedicated to applications that boot in
SPI mode (Extended SPI, DIO-SPI or QIO-SPI) and then during the application life
need to switch to XIP mode to directly execute some code in the flash.
Using the Non Volatile Configuration Register: this is dedicated to applications that
need to boot directly in XIP mode.
Section 16: Ordering
information.
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