MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 996

• Manufacturer Part Number: MC9S12XDT512MAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512MAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.9
Read: Anytime.
Write: Anytime.
The ECLKCTL register is used to control the availability of the free-running clocks and the free-running
clock divider.
998
EDIV[1:0]
NCLKX2
Reset
NECLK
1. Reset values in emulation modes are identical to those of the target mode.
Field
1–0
7
6
NS
NX
SS
ES
ST
EX
W
R
1
Dependent
NECLK
Mode
No ECLK — This bit controls the availability of a free-running clock on the ECLK pin. Clock output is always
active in emulation modes and if enabled in all other operating modes.
0 ECLK enabled
1 ECLK disabled
No ECLKX2 — This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed
rate of twice the internal bus clock. Clock output is always active in emulation modes and if enabled in all other
operating modes.
0 ECLKX2 is enabled
1 ECLKX2 is disabled
Free-Running ECLK Divider — These bits determine the rate of the free-running clock on the ECLK pin. The
usage of the bits is shown in
programmed in all other operating modes.
ECLK Control Register (ECLKCTL)
0
1
0
0
1
0
7
= Unimplemented or Reserved
NCLKX2
1
1
1
1
1
1
1
6
Figure 24-11. ECLK Control Register (ECLKCTL)
Table 24-12. ECLKCTL Field Descriptions
0
0
0
0
0
0
0
0
5
MC9S12XDP512 Data Sheet, Rev. 2.21
Table
24-13. Divider is always disabled in emulation modes and active as
0
0
0
0
0
0
0
0
4
Description
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
EDIV1
0
0
0
0
0
0
0
1
Freescale Semiconductor
EDIV0
0
0
0
0
0
0
0
0
Single-Chip
Single-Chip
Single-Chip
Expanded
Expanded
Emulation
Emulation
Special
Special
Normal
Normal
Mode
Test