MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 516
MC9S12XDT512MAA
Manufacturer Part Number
MC9S12XDT512MAA
Description
Manufacturer
Freescale
Datasheet
1.MC9S12XDT512MAA.pdf
(1348 pages)
Specifications of MC9S12XDT512MAA
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
59
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XDT512MAA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 12 Serial Peripheral Interface (S12SPIV4)
This is a high level description only, detailed descriptions of operating modes are contained in
Section 12.4.7, “Low Power Mode
12.1.4
Figure 12-1
data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.
516
•
SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit
located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in
run mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock
generation turned off. If the SPI is configured as a master, any transmission in progress stops, but
is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and
transmission of a byte continues, so that the slave stays synchronized to the master.
Stop mode
The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a
master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI
is configured as a slave, reception and transmission of a byte continues, so that the slave stays
synchronized to the master.
Block Diagram
gives an overview on the SPI architecture. The main parts of the SPI are status, control and
Options”.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
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