MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 706

• Manufacturer Part Number: MC9S12XDT512MAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512MAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 19 S12X Debug (S12XDBGV2) Module
(DBGXCTL)”. Comparators must be enabled by setting the comparator enable bit in the associated
DBGXCTL control register.
19.3.1.11 Comparator Register Descriptions
Each comparator has a bank of registers that are visible through an 8-byte window in the DBG module
register address map. Comparators A and C consist of 8 register bytes (3 address bus compare registers, 2
data bus compare registers, 2 data bus mask registers and a control register).
Comparators B and D consist of 4 register bytes (3 address bus compare registers and a control register).
Each set of comparator registers is accessible in the same 8-byte window of the register address map and
can be accessed using the COMRV bits in the DBGC1 register. If the Comparators B or D are accessed
through the 8-byte window, then only the address and control bytes are visible, the 4 bytes associated with
data bus and data bus masking read as 0 and cannot be written. Furthermore the control registers for
comparators B and D differ from those of comparators A and C.
708
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SC[3:0]
Field
3–0
0x0028
State Control Bits — These bits select the targeted next state while in State3, based upon the match event.
The trigger priorities described in
the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final state
has priority over all other matches.
Match2 triggers to State2....... Match0 triggers to final state....... Other matches have no effect
Match3 triggers to State2....... Match1 triggers to final state....... Other matches have no effect
Match1 triggers to State1....... Match3 triggers to State2....... Other matches have no effect
Table 19-25. State3 Sequencer Next State Selection
CONTROL
Match0 triggers to final state....... Other matches have no effect
Match1 triggers to final state....... Other matches have no effect
Match2 triggers to final state....... Other matches have no effect
Match3 triggers to final state....... Other matches have no effect
Table 19-24. DBGSCR3 Field Descriptions
Table 19-26. Comparator Register Layout
Match0 triggers to State1....... Other matches have no effect
Match1 triggers to State1....... Other matches have no effect
Match0 triggers to State2....... Other matches have no effect
Match1 triggers to State2....... Other matches have no effect
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 19-38
Any match triggers to final state
Any match triggers to state1
Any match triggers to state2
dictate that in the case of simultaneous matches, the match on
Description
Reserved
Reserved
Description
Read/Write
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