MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 771

• Manufacturer Part Number: MC9S12XDT512MAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512MAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

execution stage of the instruction queue a transition to the disarmed state0 occurs, ending the debug session
and generating a breakpoint, if breakpoints are enabled. External tagging is only possible in device
emulation modes.
20.4.3.4
The XGATE S/W breakpoint request issues a forced breakpoint request to the S12XCPU immediately
independent of S12XDBG settings and triggers the state sequencer into the disarmed state. Active tracing
sessions are terminated immediately, thus if tracing has not yet begun, no trace information is stored.
XGATE generated breakpoints are independent of the DBGBRK bits. The XGSBPE bit in DBGC1
determines if the XGATE S/W breakpoint function is enabled. The BDM bit in DBGC1 determines if the
XGATE requested breakpoint causes the system to enter BDM Mode or initiate a software interrupt (SWI).
20.4.3.5
Independent of comparator matches or external tag signals it is possible to initiate a tracing session and/or
breakpoint by writing to the TRIG bit in DBGC1. This triggers the state sequencer into the Final State and
issues a forced breakpoint request to both S12XCPU and XGATE.
20.4.3.6
In case of simultaneous triggers, the priority is resolved according to
trigger is suppressed. It is thus possible to miss a lower priority trigger if it occurs simultaneously with a
trigger of a higher priority. The trigger priorities described in
simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0]
encoding ensures that a match leading to final state has priority over all other matches independent of
current state sequencer state. When configured for range modes a simultaneous match of comparators A
and C generates an active match0 whilst match2 is suppressed.
Freescale Semiconductor
Highest
Priority
Lowest
Trigger On XGATE S/W Breakpoint Request
Immediate Trigger
Trigger Priorities
Match0 (force or tag hit)
Match1 (force or tag hit)
Match2 (force or tag hit)
Match3 (force or tag hit)
External TAGHI/TAGLO
Source
XGATE
TRIG
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 20-38. Trigger Priorities
Immediate forced breakpoint......(Tracing terminated immediately).
Trigger to next state as defined by state control registers
Trigger to next state as defined by state control registers
Trigger to next state as defined by state control registers
Trigger to next state as defined by state control registers
Table 20-38
Enter Final State
Enter State0
Chapter 20 S12X Debug (S12XDBGV3) Module
Table
Action
dictate that in the case of
20-38. The lower priority
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