MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 794

• Manufacturer Part Number: MC9S12XDT512MAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512MAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 21 External Bus Interface (S12XEBIV2)
The following terminology is used:
21.4.2.2.1
796
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (internal read)
DATA[15:0] (external read)
R/W
‘addr’ — value(ADDRx); small letters denote the logic values at the respective pins
‘x’ — Undefined output pin values
‘z’ — Tristate pins
‘?’ — Dependent on previous access (read or write); IVDx: ‘ivd’ or ‘x’; DATAx: ‘data’ or ‘z’
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (internal read)
DATA[15:0] (external read)
R/W
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (internal read)
DATA[15:0] (external read)
R/W
Read Access Timing
...
...
...
...
...
...
...
addr 0
high
?
?
1
Table 21-11. Read Access (n–1 Cycles)
Table 21-10. Read Access (2 Cycles)
...
...
...
...
...
...
...
...
...
...
...
...
...
...
1
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 21-9. Read Access (1 Cycle)
iqstat-1
acc 0
low
addr 0
addr 0
?
1
z
z
high
high
?
?
1
?
?
1
1
1
addr 0
iqstat -1
high
iqstat-1
acc 0
acc 0
z
z
1
low
low
Access #0
Access #0
Access #0
?
z
z
1
?
z
z
1
2
iqstat 0
000
low
addr 0
addr 1
data 0
x
z
z
1
high
high
z
1
z
z
1
2
2
addr 0
iqstat 0
iqstat 0
high
acc 1
ivd 0
z
z
1
000
low
low
z
z
1
x
z
z
1
3
0000
000
data 0
low
addr 2
data 1
addr 1
x
z
z
1
high
high
Access #1
Access #1
z
1
z
1
...
...
...
...
...
...
...
...
3
3
Freescale Semiconductor
iqstat 1
acc 2
acc 1
ivd 0
ivd 1
0000
low
low
data 0
addr 1
z
z
1
z
z
1
high
Access #1
z
1
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
n
acc 1
ivd 0
0000
low
z
z
1
...
...
...
...
...
...
...
...