MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 559

• Manufacturer Part Number: MC9S12XDT512MAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512MAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

14.3.2
This section describes all the VREG_3V3 registers and their individual bits.
14.3.2.1
The VREGHTCL is reserved for test purposes. This register should not be written.
14.3.2.2
The VREGCTRL register allows the configuration of the VREG_3V3 low-voltage detect features.
Freescale Semiconductor
Reset
Reset
LVDS
Field
LVIE
LVIF
2
1
0
W
W
R
R
Register Descriptions
Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect.
0 Input voltage V
1 Input voltage V
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
Note: On entering the Reduced Power Mode the LVIF is not cleared by the VREG_3V3.
HT Control Register (VREGHTCL)
Control Register (VREGCTRL)
0
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
DDA
DDA
Figure 14-2. HT Control Register (VREGHTCL)
is above level V
is below level V
Figure 14-3. Control Register (VREGCTRL)
Table 14-3. VREGCTRL Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
0
0
5
5
LVIA
LVID
and FPM.
or RPM or shutdown mode.
0
0
0
0
4
4
Description
0
0
0
0
3
3
Chapter 14 Voltage Regulator (S12VREG3V3V5)
LVDS
0
0
0
2
2
LVIE
0
0
0
1
1
LVIF
0
0
0
0
0
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