MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 378

• Manufacturer Part Number: MC9S12XDT512MAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512MAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
In this way, the output of the PWM will always be either the old waveform or the new waveform, not some
variation in between. If the channel is not enabled, then writes to the period register will go directly to the
latches as well as the buffer.
See
To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA,
or SB) and multiply it by the value in the period register for that channel:
For boundary case programming values, please refer to
Read: Anytime
Write: Anytime
8.3.2.14
There is a dedicated duty register for each channel. The value in this register determines the duty of the
associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value
a match occurs and the output changes state.
The duty registers for each channel are double buffered so that if they change while the channel is enabled,
the change will NOT take effect until one of the following occurs:
In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform,
not some variation in between. If the channel is not enabled, then writes to the duty register will go directly
to the latches as well as the buffer.
378
Reset
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•
•
•
•
Section 8.4.2.3, “PWM Period and Duty”
W
R
Left aligned output (CAEx = 0)
PWMx Period = Channel Clock Period * PWMPERx Center Aligned Output (CAEx = 1)
The effective period ends
The counter is written (counter resets to $00)
The channel is disabled
PWMx Period = Channel Clock Period * (2 * PWMPERx)
Bit 7
PWM Channel Duty Registers (PWMDTYx)
1
7
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active period due to the double
buffering scheme.
Figure 8-15. PWM Channel Period Registers (PWMPERx)
1
6
6
MC9S12XDP512 Data Sheet, Rev. 2.21
1
5
5
for more information.
NOTE
1
4
4
Section 8.4.2.8, “PWM Boundary
1
3
3
1
2
2
Freescale Semiconductor
1
1
1
Cases”.
Bit 0
1
0