MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 836

• Manufacturer Part Number: MC9S12XDT512MAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512MAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.15 Port K Data Register (PORTK)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
22.3.2.16 Port K Data Direction Register (DDRK)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
This register controls the data direction for port K. When Port K is operating as a general purpose I/O port,
DDRK determines whether each pin is an input or output. A logic level “1” causes the associated port pin
to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
838
PK[7:0]
Reset
Reset
Func.
Field
7–0
Alt.
W
W
R
R
ROMCTL
DDRK7
EWAIT
Port K — Port K pins 7–0 are associated with external bus control signals and internal memory expansion
emulation pins. These include ADDR22-ADDR16, No-Access (NOACC), External Wait (EWAIT) and instruction
pipe signals IQSTAT3-IQSTAT0. Bits 6-0 carry the external addresses in all expanded modes. In emulation or
special test mode with internal visibility enabled the address is multiplexed with the alternate functions NOACC
and IQSTAT on the respective pins. In single-chip modes the port pins can be used as general-purpose I/O. If
the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port
register, otherwise the buffered pin input state is read.
PK7
or
0
0
7
7
ADDR22
NOACC
DDRK6
PK6
mux
0
0
6
6
Figure 22-18. Port K Data Direction Register (DDRK)
Figure 22-17. Port K Data Register (PORTK)
Table 22-19. PORTK Field Descriptions
ADDR21
DDRK5
MC9S12XDP512 Data Sheet, Rev. 2.21
PK5
0
0
5
5
ADDR20
DDRK4
PK4
0
0
4
4
Description
ADDR19
IQSTAT3
DDRK3
PK3
mux
0
0
3
3
ADDR18
IQSTAT2
DDRK2
PK2
mux
0
0
2
2
ADDR17
IQSTAT1
DDRK1
Freescale Semiconductor
PK1
mux
0
0
1
1
ADDR16
IQSTAT0
DDRK0
PK0
mux
0
0
0
0