MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 685
MC9S12XDT512MAA
Manufacturer Part Number
MC9S12XDT512MAA
Description
Manufacturer
Freescale
Datasheet
1.MC9S12XDT512MAA.pdf
(1348 pages)
Specifications of MC9S12XDT512MAA
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
59
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XDT512MAA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Due to internal visibility of CPU accesses the CPU will be halted during XGATE or BDM access to any
PRR. This rule applies also in normal modes to ensure that operation of the device is the same as in
emulation modes.
A summary of PRR accesses:
Freescale Semiconductor
•
•
•
An aligned word access to a PRR will take 2 bus cycles.
A misaligned word access to a PRRs will take 4 cycles. If one of the two bytes accessed by the
misaligned word access is not a PRR, the access will take only 3 cycles.
A byte access to a PRR will take 2 cycles.
PRR Name
MMCCTL0
MMCCTL1
ECLKCTL
Reserved
Reserved
EBICTL0
EBICTL1
PORTC
PORTD
PORTB
PORTE
PORTK
PORTA
RDRIV
MODE
DDRA
DDRB
DDRC
DDRD
DDRE
PUCR
DDRK
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 18-23. PRR Listing
PRR Local Address
0x000C
0x000D
0x001C
0x001D
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000E
0x000F
0x0012
0x0013
0x0032
0x0033
Chapter 18 Memory Mapping Control (S12XMMCV3)
PRR Location
MMC
MMC
MMC
MMC
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
EBI
EBI
685
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