MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 211

• Manufacturer Part Number: MC9S12XDT512MAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512MAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

6.8.1.8
In this mode the result of an operation between two registers is stored in one of the registers used as
operands.
RD = RD RS is the general register to register format, with register RD being the first operand and RS
the second. RD and RS can be any of the 8 general purpose registers R0 … R7. If R0 is used as the
destination register, only the condition code flags are updated. This addressing mode is used only for shift
operations with a variable shift value
Examples:
6.8.1.9
In this mode the result of an operation between two or three registers is stored into a third one.
RD = RS1 RS2 is the general format used in the order RD, RS1, RS1. RD, RS1, RS2 can be any of the
8 general purpose registers R0 … R7. If R0 is used as the destination register RD, only the condition code
flags are updated. This addressing mode is used for all arithmetic and logical operations.
Examples:
6.8.1.10
A 9-bit signed word address offset is included in the instruction word. This addressing mode is used for
conditional branch instructions.
Examples:
6.8.1.11
An 11-bit signed word address offset is included in the instruction word. This addressing mode is used for
the unconditional branch instruction.
Examples:
6.8.1.12
(RS, #offset5) provides an unsigned offset from the base register.
Examples:
Freescale Semiconductor
LSL
LSR
ADC
SUB
BCC
BEQ
BRA
LDB
STW
Dyadic Addressing (DYA)
Triadic Addressing (TRI)
Relative Addressing 9-Bit Wide (REL9)
Relative Addressing 10-Bit Wide (REL10)
Index Register plus Immediate Offset (IDO5)
R4,R5
R4,R5
R5,R6,R7
R5,R6,R7
REL9
REL9
REL10
R4,(R1,#offset)
R4,(R1,#offset)
; R4 = R4 << R5
; R4 = R4 >> R5
MC9S12XDP512 Data Sheet, Rev. 2.21
; R5 = R6 + R7 + Carry
; R5 = R6 - R7
; PC = PC + 2 + (REL9 << 1)
; PC = PC + 2 + (REL9 << 1)
; PC = PC + 2 + (REL10 << 1)
; loads a byte from R1+offset into R4
; stores R4 as a word to R1+offset
Chapter 6 XGATE (S12XGATEV2)
211