MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 1029

• Manufacturer Part Number: MC9S12XDT512MAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512MAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

24.0.7
24.0.7.1
The BKGD pin is associated with the S12X_BDM and S12X_EBI modules. During reset, the
BKGD pin is used as MODC input.
24.0.7.2
Port A pins PA[7:0] and Port B pins PB[7:0] can be used for either general-purpose I/O.
24.0.7.3
Port E pins PE[7:2] can be used for either general-purpose I/O or with the alternative functions.
Port E pin PE[7] an be used for either general-purpose I/O or as the free-running clock ECLKX2
output running at the core clock rate. The clock output is always enabled in emulation modes.
Port E pin PE[4] an be used for either general-purpose I/O or as the free-running clock ECLK
output running at the bus clock rate or at the programmed divided clock rate. The clock output is
always enabled in emulation modes.
Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-
sensitive IRQ interrupt input. IRQ will be enabled by setting the IRQEN configuration bit
(Section 24.0.5.10, “IRQ Control Register
code register. It is inhibited at reset so this pin is initially configured as a simple input with a pull-
up.
Port E pin PE[0] can be used for either general-purpose input or as the level-sensitive XIRQ
interrupt input. XIRQ can be enabled by clearing the X-bit in the CPU’s condition code register. It
is inhibited at reset so this pin is initially configured as a high-impedance input with a pull-up.
24.0.7.4
Port K pins PK[7:0] can be used for either general-purpose I/O.
of Modules
Number
5
4
3
2
1
Ports
BKGD Pin
Port A and B
Port E
Port K
CAN0
Table 24-61. Module Implementations on Derivatives
yes
yes
yes
yes
yes
CAN1
yes
yes
yes
—
—
MSCAN Modules
CAN2
(IRQCR)”) and clearing the I-bit in the CPU’s condition
yes
yes
—
—
—
CAN3
yes
—
—
—
—
CAN4
yes
yes
yes
yes
—
SPI0
yes
yes
yes
—
—
SPI Modules
SPI1
yes
yes
—
—
—
SPI2
yes
—
—
—
—