FW82801EB Intel, FW82801EB Datasheet - Page 579

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

High-Precision Event Timer Registers
Intel
®
Table 174. Memory-Mapped Registers
82801EB ICH5 / 82801ER ICH5R Datasheet
The timer registers are memory-mapped in a non-indexed scheme. This allows the processor to
directly access each register without having to use an index register. The timer register space is
1024 bytes. The registers are generally aligned on 64-bit boundaries to simplify implementation
with IA64 processors. There are four possible memory address ranges beginning at
1) FED0_0000h, 2) FED0_1000h, 3) FED0_2000h., 4) FED0_4000h. The choice of address range
will be selected by configuration bits in General Control register (offset D0h) in Device 31,
Function 0.
Behavioral Rules:
1. Software must not attempt to read or write across register boundaries. For example, a 32-bit
2. Software should not write to read-only registers.
3. Software should not expect any particular or consistent value when reading reserved registers
028–0EFh
0F0–0F7h
0F8–0FFh
160–3FFh
000–007h
008–00Fh
010–017h
018–01Fh
020–027h
100–107h
108–10Fh
120–127h
128–12Fh
130–13Fh
140–147h
148–14Fh
150–15Fh
access should be to offset x0h, x4h, x8h, or xCh. 32-bit accesses should not be to 01h, 02h,
03h, 05h, 06h, 07h, 09h, 0Ah, 0Bh, 0Dh, 0Eh, or 0Fh. Any accesses to these offsets will result
in an unexpected behavior, and may result in a master abort. However, these accesses should
not result in system hangs. 64-bit accesses can only be to x0h and must not cross 64-bit
boundaries.
or bits.
110–11Fh
Offset
TIM1_COMP
TIM2_COMP
TIM3_COMP
TIM1_CONF
TIM2_CONF
TIM3_CONF
GEN_CONF
GINTR_STA
MAIN_CNT
Mnemonic
GCAP_ID
—
—
—
—
—
—
—
—
General Capabilities and Identification
Reserved
General Configuration
Reserved
General Interrupt Status
Reserved
Main Counter Value
Reserved
Timer 0 Configuration and Capabilities
Timer 0 Comparator Value
Reserved
Timer 1 Configuration and Capabilities
Timer 1 Comparator Value
Reserved
Timer 2 Configuration and Capabilities
Timer 2 Comparator Value
Reserved
Reserved
Register
High-Precision Event Timer Registers
0429B17F80
86A201h
Default
0000h
0000h
N/A
N/A
N/A
N/A
N/A
N/A
N/A
—
—
—
—
—
—
—
—
R/WC
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
17
RO
—
—
—
—
—
—
—
—
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