FW82801EB Intel, FW82801EB Datasheet - Page 398

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.10.9
398
Note: If the corresponding _EN bit is set when the _STS bit is set, the ICH5 will cause an SMI# (except
SMI_STS—SMI Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
bits 8–10 and 12, which do not need enable bits since they are logic ORs of other registers that
have enable bits). The ICH5 uses the same GPE0_EN register (I/O address: PMBase+2Ch) to
enable/disable both SMI and ACPI SCI general purpose input events. ACPI OS assumes that it
owns the entire GPE0_EN register per ACPI spec. Problems arise when some of the general-
purpose inputs are enabled as SMI by BIOS, and some of the general purpose inputs are enabled
for SCI. In this case ACPI OS turns off the enabled bit for any GPIx input signals that are not
indicated as SCI general-purpose events at boot, and exit from sleeping states. BIOS should define
a dummy control method which prevents the ACPI OS from clearing the SMI GPE0_EN bits.
31:19
Bit
18
17
16
15
14
13
12
Reserved
INTEL_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each of the SMI status
bits in the Intel-Specific USB2 SMI Status Register ANDed with the corresponding enable bits. This
bit will not be active if the enable bits are not set. Writes to this bit will have no effect.
LEGACY_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each of the SMI status
bits in the USB2 Legacy Support Register ANDed with the corresponding enable bits. This bit will
not be active if the enable bits are not set. Writes to this bit will have no effect.
SMBus SMI Status (SMBUS_SMI_STS) — R/WC. Software clears this bit by writing a 1 to it.
0 = This bit is set from the 64 KHz clock domain used by the SMBus. Software must wait at least
1 = Indicates that the SMI# was caused by:
SERIRQ_SMI_STS — RO.
0 = SMI# was not caused by the SERIRQ decoder. This is not a sticky bit.
1 = Indicates that the SMI# was caused by the SERIRQ decoder.
PERIODIC_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set at the rate determined by the PER_SMI_SEL bits. If the PERIODIC_EN bit is also
TCO_STS — RO.
0 = SMI# not caused by TCO logic.
1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake event.
Device Monitor Status (DEVMON_STS) — RO.
0 = SMI# not caused by Device Monitor.
1 = Set under any of the following conditions:
15.63 us after the initial assertion of this bit before clearing it.
1. The SMBus Slave receiving a message, or
2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the
3. The SMBus Slave receiving a Host Notify message and the HOST_NOTIFY_INTREN and
4. The Intel
set, the ICH5 generates an SMI#.
– Any of the DEV[7:4]_TRAP_STS bits are set and the corresponding DEV[7:4]_TRAP_EN
– Any of the DEVTRAP_STS bits are set and the corresponding DEVTRAP_EN bits are
bits are also set.
SMBALERT_DIS bit is cleared, or
the SMB_SMI_EN bits are set, or
also set.
PMBASE + 34h
0000h
No
Core
®
ICH5 detecting the SMLINK_SLAVE_SMI command while in the S0 state.
Description
Intel
Attribute:
Size:
Usage:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RO, R/WC
32-bit
ACPI or Legacy