FW82801EB Intel, FW82801EB Datasheet - Page 143

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.12.1.4
5.12.1.5
5.12.1.6
5.12.2
5.12.2.1
Intel
®
Table 55. NMI Sources
Table 56. DP Signal Differences
82801EB ICH5 / 82801ER ICH5R Datasheet
Stop Clock Request and CPU Sleep
NMI (Non-Maskable Interrupt)
Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in
(STPCLK# and CPUSLP#)
The ICH5 power management logic controls these active-low signals. Refer to
more information on the functionality of these signals.
CPU Power Good (CPUPWRGOOD)
This signal is connected to the processor’s PWRGOOD input. This is an open-drain output signal
(external pull-up resistor required) that represents a logical AND of the ICH5’s PWROK and
VRMPWRGD signals.
Dual-Processor Issues
Signal Differences
In dual-processor designs, some of the processor signals are unused or used differently than for
uniprocessor designs.
SERR# goes active (either internally, externally
via SERR# signal, or via message from MCH)
IOCHK# goes active via SERIRQ# stream
(ISA system Error)
A20M# / A20GATE
STPCLK#
FERR# / IGNNE#
Signal
Cause of NMI
Generally not used, but still supported by Intel
Used for S1 State as well as preparation for entry to S3–S5
Also allows for THERM# based throttling (not via ACPI control methods). Should be
connected to both processors.
Generally not used, but still supported by ICH5.
Can instead be routed to generate an SCI, through the
NMI2SCI_EN bit (Device 31:Function 0, offset 4E, bit 11).
Can instead be routed to generate an SCI, through the
NMI2SCI_EN bit (Device 31:Function 0, offset 4E, bit 11).
Difference
®
ICH5.
Comment
Functional Description
Section 5.13
Table
for
55.
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