FW82801EB Intel, FW82801EB Datasheet - Page 301

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Hub Interface to PCI Bridge Registers
(D30:F0)
8.1
.
Intel
®
Table 140. Hub Interface PCI Register Address Map (HUB-PCI—D30:F0) (Sheet 1 of 2)
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: Address locations that are not shown in
The hub interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the
ICH5 implements the buffering and control logic between PCI and the hub interface. The
arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must
decode the ranges for the hub interface. All register contents will be lost when core well power is
removed.
PCI Configuration Registers (D30:F0)
for details).
1E–1Fh
00–01h
02–03h
04–05h
06–07h
20–21h
22–23h
24–25h
26–27h
30–31h
Offset
0Ah
0Bh
0Dh
0Eh
1Ah
1Bh
1Ch
1Dh
08h
18h
19h
PREF_MEM_BASE
PREF_MEM_MLT
SUB_BUS_NUM
PBUS_NUM
SBUS_NUM
IOBASE_HI
Mnemonic
MEMBASE
HEADTYP
PCICMD
SECSTS
MEMLIM
IOBASE
PCISTS
IOLIM
PMLT
SMLT
SCC
BCC
VID
DID
RID
I/O Base
I/O Base Upper 16 Bits
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Sub Class Code
Base Class Code
Primary Master Latency Timer
Header Type
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Secondary Master Latency Timer
I/O Limit
Secondary Status
Memory Base
Memory Limit
Prefetchable Memory Base
Prefetchable Memory Limit
Table 140
Hub Interface to PCI Bridge Registers (D30:F0)
Register Name
should be treated as Reserved (see
See register
description
Default
FFF0h
FFF0h
8086h
244Eh
0001h
0080h
0280h
0000h
0000h
0000h
04h
06h
00h
01h
00h
00h
00h
00h
F0h
00h
Section 6.2
R/WC, RO
R/WC, RO
R/W, RO
R/W, RO
R/W, RO
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
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