FW82801EB Intel, FW82801EB Datasheet - Page 418

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

IDE Controller Registers (D31:F1)
10.1.4
418
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
PCISTS — PCI Status Register
(IDE—D31:F1)
Address Offset:
Default Value:
effect.
10:9
Bit
2:0
15
14
13
12
11
8
7
6
5
4
3
Detected Parity Error (DPE) — RO. Reserved as 0.
Signaled System Error (SSE) — RO. Reserved as 0.
Received Master Abort (RMA) — R/WC.
0 = Master abort not generated by Bus Master IDE interface function.
1 = Bus Master IDE interface function, as a master, generated a master abort.
Reserved as 0 — RO.
Signaled Target Abort (STA) — R/WC.
0 = Intel
1 = IDE interface function is targeted with a transaction that the ICH5 terminates with a target
DEVSEL# Timing Status (DEV_STS) — RO.
01 = Hardwired; however, the ICH5 does not have a real DEVSEL# signal associated with the IDE
Data Parity Error Detected (DPED) — RO. Reserved as 0.
Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
User Definable Features (UDF) — RO. Reserved as 0.
66 MHz Capable (66MHZ_CAP) — RO. Reserved as 0.
Reserved
Interrupt Status (INTS) — RO. This bit is independent of the state of the Interrupt Disable bit in the
command register.
0 = Interrupt is cleared.
1 = Interrupt/MSI is asserted.
Reserved
abort.
unit, so these bits have no effect.
®
06
0280h
ICH5 did not target abort a transaction targeting the IDE interface function.
–
07h
Intel
Description
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/WC, RO
16 bits