FW82801EB Intel, FW82801EB Datasheet - Page 501

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
NOTE: The Command Register indicates the command to be executed by the serial bus host controller. Writing
Bit
3:2
1
0
to the register causes a command to be executed.
Frame List Size — RO. The ICH5 hardwires this field to 00b because it only supports the
1024-element frame list size.
Host Controller Reset (HCRESET) — R/W. This control bit used by software to reset the host
controller. The effects of this on Root Hub registers are similar to a Chip Hardware Reset
(i.e., RSMRST# assertion and PWROK deassertion on the ICH5).
When software writes a 1 to this bit, the Host Controller resets its internal pipelines, timers, counters,
state machines, etc. to their initial value. Any transaction currently in progress on USB is
immediately terminated. A USB reset is not driven on downstream ports.
NOTE: PCI Configuration registers and Host Controller Capability Registers are not effected by this
All operational registers, including port registers and port state machines are set to their initial
values. Port ownership reverts to the companion host controller(s), with the side effects described in
the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0.
Software must re-initialize the host controller in order to return the host controller to an operational
state.
This bit is set to 0 by the Host Controller when the reset process is complete. Software cannot
terminate the reset process early by writing a 0 to this register.
Software should not set this bit to a 1 when the HCHalted bit in the USB2.0_STS register is a 0.
Attempting to reset an actively running host controller will result in undefined behavior. This reset me
be used to leave EHCI port test modes.
Run/Stop (RS) — R/W.
0 = Stop (default)
1 = Run. When set to a 1, the Host Controller proceeds with execution of the schedule. The Host
Software should not write a 1 to this field unless the host controller is in the Halted state
(i.e., HCHalted in the USBSTS register is a 1). The Halted bit is cleared immediately when the Run
bit is set.
The following table explains how the different combinations of Run and Halted should be interpreted:
Run/Stop
Memory read cycles initiated by the EHC that receive any status other than Successful will result in
this bit being cleared.
0
0
1
1
Controller continues execution as long as this bit is set. When this bit is set to 0, the Host
Controller completes the current transaction on the USB and then halts. The HCHalted bit in the
USB2.0_STS register indicates when the Host Controller has finished the transaction and has
entered the stopped state.
reset.
Halted
0
1
0
1
Interpretation
Valid- in the process of halting
Valid- halted
Valid- running
Invalid- the HCHalted bit clears immediately.
Description
EHCI Controller Registers (D29:F7)
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