FW82801EB Intel, FW82801EB Datasheet - Page 162

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.13.11.2
5.13.11.3
5.13.11.4
162
Note: To utilize the minimum DRAM power-down feature that is enabled by the SLP_S4# Assertion
Note:
SLP_S4# and Suspend-To-RAM Sequencing
The system memory suspend voltage regulator is controlled by the Glue logic
“LATCHED_BACKFEED_CUT” signal. This signal should be generated using the SLP_S4#
signal rather than the SLP_S5# signal, even if the platform does not support S4 Sleep State. The
SLP_S4# logic in the ICH5 provides a mechanism to fully cycle the power to the DRAM and/or
detect if the power is not cycled for a minimum time.
Stretch Enable bit (D31:F0:A4h bit 3), the DRAM power must be controlled by the SLP_S4#
signal.
PWROK Signal
The PWROK input should go active based on the core supply voltages becoming valid. PWROK
should go active no sooner than 100 ms after Vcc3_3 and Vcc1_5 have reached their nominal
values.
VRMPWRGD Signal
This signal is connected to the processor’s VRM and is internally AND’d with the PWROK signal
that comes from the system power supply. This saves the external AND gate found in desktop
systems.
1. SYSRESET# is recommended for implementing the system reset button. This saves external
2. If the PWROK input is used to implement the system reset button, the ICH5 does not provide
3. If a design has an active-low reset button electrically AND’d with the PWROK signal from the
4. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that are less
5. In the case of true PWROK failure, PWROK goes low first before the VRMPWRGD.
logic that is needed if the PWROK input is used. Additionally, it allows for better handling of
the SMBus and processor resets, and avoids improperly reporting power failures.
any mechanism to limit the amount of time that the processor is held in reset. The platform
must externally guarantee that maximum reset assertion specs are met.
power supply and the processor’s voltage regulator module the ICH5 PWROK_FLR bit will
be set. The ICH5 treats this internally as if the RSMRST# signal had gone active. However, it
is not treated as a full power failure. If PWROK goes inactive and then active (but RSMRST#
stays high), then the ICH5 reboots (regardless of the state of the AFTERG3 bit). If the
RSMRST# signal also goes low before PWROK goes high, then this is a full power failure,
and the reboot policy is controlled by the AFTERG3 bit.
than one RTC clock period may not be detected by the ICH5.
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet