FW82801EB Intel, FW82801EB Datasheet - Page 214

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
214
Table 100. USB Legacy Keyboard State Transitions
Current State
GateState1
GateState1
GateState1
GateState1
GateState1
GateState2
GateState2
GateState2
GateState2
GateState2
IDLE
IDLE
IDLE
IDLE
IDLE
64h / Write
64h / Write
64h / Read
60h / Write
60h / Read
60h / Write
64h / Write
64h / Write
60h / Read
64h / Read
64h / Write
64h / Read
60h / Write
60h / Read
64 / Write
Action
Data Value
Don't Care
Not D1h
Not D1h
Not FFh
D1h
XXh
D1h
FFh
XXh
N/A
N/A
N/A
N/A
N/A
N/A
GateState1
GateState2
GateState1
GateState1
GateState2
Next State
IDLE
IDLE
IDLE
IDLE
ILDE
IDLE
IDLE
IDLE
IDLE
IDLE
Intel
®
Standard D1 command. Cycle passed through to
8042. SMI# doesn't go active. PSTATE (offset C0,
bit 6) goes to 1.
Bit 3 in Config Register determines if cycle passed
through to 8042 and if SMI# generated.
Bit 2 in Config Register determines if cycle passed
through to 8042 and if SMI# generated.
Bit 1 in Config Register determines if cycle passed
through to 8042 and if SMI# generated.
Bit 0 in Config Register determines if cycle passed
through to 8042 and if SMI# generated.
Cycle passed through to 8042, even if trap enabled
in Bit 1 in Config Register. No SMI# generated.
PSTATE remains 1. If data value is not DFh or DDh
then the 8042 may chose to ignore it.
Cycle passed through to 8042, even if trap enabled
via Bit 3 in Config Register. No SMI# generated.
PSTATE remains 1. Stay in GateState1 because
this is part of the double-trigger sequence.
Bit 3 in Config space determines if cycle passed
through to 8042 and if SMI# generated. PSTATE
goes to 0. If Bit 7 in Config Register is set, then
SMI# should be generated.
This is an invalid sequence. Bit 0 in Config
Register determines if cycle passed through to
8042 and if SMI# generated. PSTATE goes to 0. If
Bit 7 in Config Register is set, then SMI# should be
generated.
Just stay in same state. Generate an SMI# if
enabled in Bit 2 of Config Register. PSTATE
remains 1.
Standard end of sequence. Cycle passed through
to 8042. PSTATE goes to 0. Bit 7 in Config Space
determines if SMI# should be generated.
Improper end of sequence. Bit 3 in Config Register
determines if cycle passed through to 8042 and if
SMI# generated. PSTATE goes to 0. If Bit 7 in
Config Register is set, then SMI# should be
generated.
Just stay in same state. Generate an SMI# if
enabled in Bit 2 of Config Register. PSTATE
remains 1.
Improper end of sequence. Bit 1 in Config Register
determines if cycle passed through to 8042 and if
SMI# generated. PSTATE goes to 0. If Bit 7 in
Config Register is set, then SMI# should be
generated.
Improper end of sequence. Bit 0 in Config Register
determines if cycle passed through to 8042 and if
SMI# generated. PSTATE goes to 0. If Bit 7 in
Config Register is set, then SMI# should be
generated.
82801EB ICH5 / 82801ER ICH5R Datasheet
Comment