FW82801EB Intel, FW82801EB Datasheet - Page 386

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.10.1
386
Note: Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but can cause an
PM1_STS—Power Management 1 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
If bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the PM1_EN register,
then the ICH5 will generate a Wake Event. Once back in an S0 state (or if already in an S0 state
when the event occurs), the ICH5 will also generate an SCI if the SCI_EN bit is set, or an SMI# if
the SCI_EN bit is not set.
SMI# or SCI.
14:12
Bit
15
11
10
9
Reserved
Wake Status (WAK_STS) — R/WC. This bit is not affected by hard resets caused by a CF9 write,
but is reset by RSMRST#.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the system is in one of the sleep states (via the SLP_EN bit) and an
If the AFTERG3_EN bit is not set and a power failure occurs without the SLP_EN bit set, the
system will return to an S0 state when power returns, and the WAK_STS bit will not be set.
If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit having been set,
the system will go into an S5 state when power returns, and a subsequent wake event will cause
the WAK_STS bit to be set. Note that any subsequent wake event would have to be caused by
either a Power Button press, or an enabled wake event that was preserved through the power
failure (enable bit in the RTC well).
Power Button Override Status (PRBTNOR_STS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set any time a Power Button Override occurs (i.e., the power button is pressed for
RTC Status (RTC_STS) — R/WC. This bit is not affected by hard resets caused by a CF9 write,
but is reset by RSMRST#.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8# signal).
Reserved
enabled wake event occurs. Upon setting this bit, the Intel
the ON state.
at least 4 consecutive seconds), or due to the corresponding bit in the SMBus slave
message. The power button override causes an unconditional transition to the S5 state, as
well as sets the AFTERG# bit. The BIOS or SCI handler clears this bit by writing a 1 to it.
This bit is not affected by hard resets via CF9h writes, and is not reset by RSMRST#. Thus,
this bit is preserved through power failures.
Additionally if the RTC_EN bit is set, the setting of the RTC_STS bit will generate a wake
event.
PMBASE + 00h
0000h
No
Bits 0
Bits 8
except Bit 11 in RTC
( ACPI PM1a_EVT_BLK )
–
–
7: Core,
15: Resume,
Intel
Description
Attribute:
Size:
Usage:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
®
ICH5 will transition the system to
R/WC
16-bit
ACPI or Legacy