FW82801EB Intel, FW82801EB Datasheet - Page 56

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Signal Description
2.8
56
Table 9.
Table 10. LPC Interface Signals
IDE Interface Signals (Sheet 2 of 2)
LPC Interface
PWDMARDY#)
SWDMARDY#)
PRDMARDY#)
SRDMARDY#)
LFRAME# /
LAD[3:0] /
LDRQ1# /
(PDWSTB /
(SDWSTB /
LDRQ0#
(PDRSTB /
(SDRSTB /
(PDSTOP)
(SDSTOP)
GPIO41
PDIOW# /
SDIOW# /
PDIOR# /
SDIOR# /
PIORDY /
SIORDY /
FB[3:0]
Name
FB4
Name
Type
I/O
O
I
Type
O
O
I
LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pull-ups are
provided.
LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.
LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or
bus master access. These signals are typically connected to external Super I/O
device. An internal pull-up resistor is provided on these signals.
LDRQ1# may optionally be used as GPI.
Primary and Secondary Disk I/O Read (PIO and Non-Ultra DMA): This is the
command to the IDE device that it may drive data onto the PDD or SDD lines. Data
is latched by the ICH5 on the deassertion edge of PDIOR# or SDIOR#. The IDE
device is selected either by the ATA register file chip selects (PDCS1# or SDCS1#,
PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA acknowledge
(PDDAK# or SDDAK#).
Primary and Secondary Disk Write Strobe (Ultra DMA Writes to Disk): This is the
data write strobe for writes to disk. When writing to disk, ICH5 drives valid data on
rising and falling edges of PDWSTB or SDWSTB.
Primary and Secondary Disk DMA Ready (Ultra DMA Reads from Disk): This is the
DMA ready for reads from disk. When reading from disk, ICH5 deasserts
PRDMARDY# or SRDMARDY# to pause burst data transfers.
Primary and Secondary Disk I/O Write (PIO and Non-Ultra DMA): This is the
command to the IDE device that it may latch data from the PDD or SDD lines. Data
is latched by the IDE device on the deassertion edge of PDIOW# or SDIOW#. The
IDE device is selected either by the ATA register file chip selects (PDCS1# or
SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA
acknowledge (PDDAK# or SDDAK#).
Primary and Secondary Disk Stop (Ultra DMA): ICH5 asserts this signal to
terminate a burst.
Primary and Secondary I/O Channel Ready (PIO): This signal will keep the
strobe active (PDIOR# or SDIOR# on reads, PDIOW# or SDIOW# on writes) longer
than the minimum width. It adds wait-states to PIO transfers.
Primary and Secondary Disk Read Strobe (Ultra DMA Reads from Disk): When
reading from disk, ICH5 latches data on rising and falling edges of this signal from
the disk.
Primary and Secondary Disk DMA Ready (Ultra DMA Writes to Disk): When writing
to disk, this is de-asserted by the disk to pause burst data transfers.
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Description
Description