FW82801EB Intel, FW82801EB Datasheet - Page 417

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

10.1.3
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
PCICMD—PCI Command Register
(IDE—D31:F1)
Address Offset:
Default Value:
15:11
Bit
10
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable (ID) — R/W.
0 = Enables the IDE controller to assert INTA# (native mode) or IRQ14/15 (legacy mode).
1 = Disable. The interrupt will be deasserted.
Fast Back to Back Enable (FBE) — RO. Reserved as 0.
SERR# Enable (SERR_EN) — RO. Reserved as 0.
Wait Cycle Control (WCC) — RO. Reserved as 0.
Parity Error Response (PER) — RO. Reserved as 0.
VGA Palette Snoop (VPS) — RO. Reserved as 0.
Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
Special Cycle Enable (SCE) — RO. Reserved as 0.
Bus Master Enable (BME) — R/W. Controls the Intel
Bus Master transfers.
Memory Space Enable (MSE) — R/W.
0 = Disables access.
1 = Enables access to the IDE Expansion memory range. The EXBAR register (Offset 24h) must
NOTE: BIOS should set this bit to a 1.
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as the
1 = Enable. Note that the Base Address register for the Bus Master registers should be
NOTES:
1. Separate bits are provided (IDE Decode Enable, in the IDE Timing register) to independently
2. When this bit is 0 and the IDE controller is in Native Mode, the Interrupt Pin Register (see
disable the Primary or Secondary I/O spaces.
Section
If an interrupt occurs while the masking is in place and the interrupt is still active when the
masking ends, the interrupt will be allowed to be asserted.
be programmed before this bit is set.
Bus Master IO registers.
programmed before this bit is set.
04h
00h
10.1.18) will be masked (the interrupt will not be asserted).
–
05h
Description
Attribute:
Size:
®
ICH5’s ability to act as a PCI master for IDE
IDE Controller Registers (D31:F1)
RO, R/W
16 bits
417