FW82801EB Intel, FW82801EB Datasheet - Page 312

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.25
312
HI1_CMD—Hub Interface 1 Command Control Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
31:21
19:16
15:14
12:10
Bit
9:4
3:1
20
13
0
Reserved
HP Unsupported (HPUN) — R/W.
1 = Intel
Hub Interface Timeslice (HI_TMSL) — R/W. This field sets the HI arbiter time-slice value with 4
base-clock granularity. A value of 0h means that the time-slice is immediately expired and that the
ICH5 will allow the other master’s request to be serviced after every message.
Hub Interface Width (HI_Width) — RO. This field is hardwired to 00b, indicating that the hub
interface is 8 bits wide.
Hub Interface Rate Valid (HI_Rate_Val) — RO. Hardwired to 1.
Hub Interface Rate (HI_Rate) — RO. Encoded value representing the clock-to-transfer rate of the
HI1 interface:
1:4 = 010b
The value is loaded at reset by sampling the capability of the device connected to the HI1 port. The
value for this field is fixed for 4X mode only.
Reserved.
Max Data (MAXD) — RO. Hardwired to 001b. This field specifies the maximum amount of data that
the ICH5 is allowed to burst in one packet on the hub interface. The ICH5 will always perform 64-
byte bursts.
Reserved
Parity Error Response bit in D30:F0:04h bit 6.
®
ICH5 will not check parity on the hub interface even if enabled to do so according to the
40
76202802h
–
43h
Description
Intel
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W, RO
32 bits