FW82801EB Intel, FW82801EB Datasheet - Page 535

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

15.1.3
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
PCICMD—PCI Command Register
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
PCICMD is a 16-bit control register. Refer to the PCI Local Bus Specification, Revision 2.3 for
complete details on each bit.
15:11
Bit
10
9
8
7
6
5
4
3
2
1
0
Reserved. Read 0.
Interrupt Disable (ID) — R/W.
0 = The INTx# signals may be asserted and MSIs may be generated.
1 = The AC ‘97 controller’s INTx# signal will be de-asserted and it may not generate MSIs.
Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.
SERR# Enable (SERR_EN) — RO. Not implemented. Hardwired to 0.
Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0.
Parity Error Response (PER) — RO. Not implemented. Hardwired to 0.
VGA Palette Snoop (VPS). Not implemented. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to 0.
Special Cycle Enable (SCE). Not implemented. Hardwired to 0.
Bus Master Enable (BME) — R/W. Controls standard PCI bus mastering capabilities.
0 = Disable
1 = Enable
Memory Space Enable (MSE) — R/W. Enables memory space addresses to the AC ’97 audio
controller.
0 = Disable
1 = Enable
I/O Space Enable (IOSE) — R/W. This bit controls access to the AC ’97 audio controller I/O space
registers.
0 = Disable (Default).
1 = Enable access to I/O space. The Native PCI Mode Base Address register should be
NOTE: This bit becomes writable when the IOSE bit in offset 41h is set. If at any point software
programmed prior to setting this bit.
decides to clear the IOSE bit, software must first clear the IOS bit.
04
0000h
No
–
05h
AC ’97 Audio Controller Registers (D31:F5)
Description
Attribute:
Size:
Power Well:
R/W, RO
16 bits
Core
535