FW82801EB Intel, FW82801EB Datasheet - Page 167

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
The following rules/steps apply if the system is in a G0 state and the policy is for the ICH5 to not
reboot the system after a hardware lockup.
10. After step 8 (reset attempt), if the reset is unsuccessful, the ICH5 continues sending a message
10. If step 8 (reset attempt), is unsuccessful, the ICH5 continues sending heartbeats. The ICH5
11. This and the following rules/steps apply if the user intervention (power button press, reset,
7. If step 5 (power button press) is unsuccessful in waking the system, the ICH5 continues
8. After step 3 (unsuccessful reboot after third timeout), if a reset is attempted (using a button
9. After step 8 (reset attempt) if the reset is successful, the BIOS is run. The ICH5 continues
1. On detecting the lockup the SECOND_TO_STS bit is set. The ICH5 sends a message with the
2. After step 1, the ICH5 sends a message every heartbeat period until some external intervention
3. Rules/steps 4–10 apply if no user intervention (resets, power button presses, SMBus reset
4. After step 3 (third timeout), if the user does a Power Button Override, the system goes to an S5
5. After step 4 (power button override), if the user presses the power button again, the system
6. If step 5 (power button press) is successful in waking the system, the ICH5 continues sending
7. If step 5 (power button press) is unsuccessful in waking the system, the ICH5 continues
8. After step 3 (3
9. If step 8 (reset attempt) is successful, the BIOS is run. The ICH5 continues sending heartbeats
sending a message every heartbeat period. The ICH5 does not attempt to automatically reboot
again. The ICH5 starts sending a message every heartbeat period (30–32 seconds). The
heartbeats continue until some external intervention occurs (reset, power failure, etc.).
(See note 3)
that pulses PWROK low or via the message on the SMBus slave I/F), the ICH5 attempts to
reset the system.
sending a message every heartbeat period until the BIOS clears the SECOND_TO_STS bit.
(See note 2)
every heartbeat period. The ICH5 does not attempt to reboot the system again without external
intervention. (See note 3)
Watchdog (WD) Event status bit set (and any other bits that must also be set). This message is
sent as soon as the lockup is detected, and is sent with the next (incremented) sequence
number.
occurs.
messages) occur after a third timeout of the watchdog timer. If the intervention occurs before
the third timeout, then jump to rule/step11.
state. The ICH5 continues sending heartbeats at this point.
should wake to an S0 state and the processor should start executing the BIOS.
heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2)
sending heartbeats. The ICH5 does not attempt to reboot the system again until some external
intervention occurs (reset, power failure, etc.). (See note 3)
the message on the SMBus slave I/F), the ICH5 attempts to reset the system.
until the BIOS clears the SECOND_TO_STS bit. (See note 2)
does not attempt to reboot the system again without external intervention. Note: A system that
has locked up and can not be restarted with power button press is probably broken (bad power
supply, short circuit on some bus, etc.)
SMBus message, etc.) occur prior to the third timeout of the watchdog timer.
rd
timeout), if a reset is attempted (using a button that pulses PWROK low or via
Functional Description
167