FW82801EB Intel, FW82801EB Datasheet - Page 158

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.13.9.3
5.13.9.4
5.13.9.5
158
THRMTRIP# Signal
PME# (PCI Power Management Event)
The PME# signal comes from a PCI device to request that the system be restarted. The PME#
signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs when the PME#
signal goes from high to low. No event is caused when it goes from low to high.
In the EHCI controller, there is an internal PME_B0 bit. This is separate from the external PME#
signal and can cause the same effect.
SYS_RESET# Signal
SYS_RESET# on the ICH5 is used to eliminate extra glue logic on the board. Before the addition
of this pin, a system reset was activated by external glue forcing the PWROK signal low after the
reset button was pressed. This pin eliminates the need for that glue.
When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the ICH5
attempts to perform a “graceful” reset, by waiting up to 25 ms for the SMBus to go idle. If the
SMBus is idle when the pin is detected active, the reset occurs immediately; otherwise, the counter
starts. If at any point during the count the SMBus goes idle the reset occurs. If, however, the
counter expires and the SMBus is still active, a reset is forced upon the system even though activity
is still occurring.
Once the reset is asserted, it remains asserted for approximately 1 ms regardless of whether the
SYSRESET# input remains asserted or not. It cannot occur again until SYS_RESET# has been
detected inactive after the debounce logic, and the system is back to a full S0 state with PCIRST#
inactive.
If THRMTRIP# goes active, the processor is indicating an overheat condition, and the ICH5
immediately transitions to an S5 state. However, since the processor has overheated, it does not
respond to the ICH5’s STPCLK# pin with a stop grant special cycle. Therefore, the ICH5 does not
wait for one. Immediately upon seeing THRMTRIP# low, the ICH5 initiates a transition to the S5
state, drive SLP_S3#, SLP_S4#, SLP_S5# low, and set the CTS bit. The transition looks like a
power button override.
It is extremely important that when a THRMTRIP# event occurs, the ICH5 power down
immediately without following the normal S0 -> S5 path. This path may be taken in parallel, but
ICH5 must immediately enter a power down state. It does this by driving SLP_S3#, SLP_S4#, and
SLP_S5# immediately after sampling THRMTRIP# active.
If the processor is running extremely hot and is heating up, it is possible (although very unlikely)
that components around it, such as the ICH5, are no longer executing cycles properly. Therefore, if
THRMTRIP# fires, and the ICH5 is relying on state machine logic to perform the power down, the
state machine may not be working, and the system will not power down.
The ICH5 follows this flow for THRMTRIP#.
1. At boot (PCIRST# low), THRMTRIP# ignored.
2. After power-up (PCIRST# high), if THRMTRIP# sampled active, SLP_S3#, SLP_S4#, and
3. Until sleep machine enters the S5 state, SLP_S3#, SLP_S4#, and SLP_S5# stay active, even if
4. If S5 state reached, go to step #1, otherwise stay here. If the ICH5 never reaches S5, the ICH5
SLP_S5# fire, and normal sequence of sleep machine starts.
THRMTRIP# is now inactive. This is the equivalent of “latching” the thermal trip event.
does not reboot until power is cycled.
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet