FW82801EB Intel, FW82801EB Datasheet - Page 490

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

EHCI Controller Registers (D29:F7)
13.1.24
490
FL_ADJ—Frame Length Adjustment Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
This feature is used to adjust any offset from the clock source that generates the clock that drives
the SOF counter. When a new value is written into these six bits, the length of the frame is adjusted.
Its initial programmed value is system dependent based on the accuracy of hardware USB clock
and is initialized by system BIOS. This register should only be modified when the HChalted bit in
the USB2.0_STS register is a 1. Changing value of this register while the host controller is
operating yields undefined results. It should not be reprogrammed by USB system software unless
the default or BIOS programmed values are incorrect, or the system is restoring the register while
returning from a suspended state.
Bit
7:6
5:0
Reserved — RO. These bits are reserved for future use and should read as 00b.
Frame Length Timing Value — R/W. Each decimal value change to this register corresponds to
16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a
SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal
32 (20h), which gives a SOF cycle time of 60000.
Frame Length
(# 480 MHz Clocks)
59488
59504
59520
…
59984
60000
…
60480
60496
61h
20h
FLADJ Value
decimal (hex)
0 (00h)
1 (01h)
2 (02h)
31 (1Fh)
32 (20h)
62 (3Eh)
63 (3Fh)
Intel
Description
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
8 bits