TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 99

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

9 9 o f 2 2 6
TimingMode
(Address 0x3A60)
LineTimingChannel
(Address 0x3A62)
TxRefSelect
(Address 0x3A64)
RxRefSelect
(Address 0x3A66)
TxPLL_Cap_Enable
(Address 0x3A68)
RxPLL_Cap_Enable
(Address 0x3A6A)
TxRefFreq
(Address 0x3A6C)
RxRefFreq
(Address 0x3A6E)
TxPLL_PowerDown
(Address 0x3A70)
RxPLL_PowerDown
(Address 0x3A72)
LineRate
(Address 0x3A52)
OC3NotOC12
(Address 0x3A5A)
Register
10.4.1 Powerup of the CDR/CS
A startup sequence for the Clock and Data Recovery / Clock Synthesis part of the PHAST-
12P is given below (all registers can be found in the CDR/CS section of the Memory Map):
•
•
•
•
•
•
Set device in software reset: Write 0x91 to RESETH (Address 0x00A0). Other clock
domains can also be set in reset now (See Memory Map).
Write 0x0000 to IndirectAccessMode (Address 0x3A26), followed by writing 0x0017 to
IndiretAccessData (Address 0x3A5E)
Write 0x0008 to IndirectAccessMode (Address 0x3A26), followed by writing 0x5000 to
IndiretAccessData (Address 0x3A5E)
Configure System Loopback (Address 0x3A22) or Facility Loopback (Address 0x3A24) if
desirable
Configure the CDRTune and PLLTune parameters (Addresses 0x3A74-0x3A7C and
0x3A7E) Refer to the Memory Map section for recommended values.
Configure the PLL’s for External or Line Timing as follows:
Select Tx Reference Clock
Select Rx Reference Clock
Enable/Disable External Capacitor for Tx
PLL
Enable/Disable External Capacitor for Rx
PLL
Select Tx PLL Reference Clock Frequency
Select Rx PLL Reference Clock Fre-
quency
STM-1/OC-3 Mode
0x0F
External Timing
N/A
N/A
0x0
0x0
0x0
STM-4/OC-12 Mode STM-1/OC-3 Mode
- Operation -
0x0E
Select timing mode channel
Enable/Disable External Capacitor for Tx
PLL
Enable/Disable External Capacitor for Rx
PLL
Select Rx PLL Reference Clock Fre-
quency
Select Line Rate of Reference Channel
Select Rx Reference Clock
0x0F
PRELIMINARY TXC-06412B-MB, Ed. 2
Line Timing
PHAST-12P Device
0x1
N/A
N/A
0x0
0x0
STM-4/OC-12 Mode
DATA SHEET
0x0E
TXC-06412B
June 2005