TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 29

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

2 9 o f 2 2 6
REFONESECCLK
REFTXCLK2P
REFTXCLK2N
REFRXCLK
REFSYSFS
REFTXFS
Symbol
RESET
Lead No. I/O/P
AB9
AB8
B21
W8
R1
R2
A4
O
I
I
I
I
I
LVCMOS
LVPECL Transmit Reference Clock #2: Reference clock for the
LVTTLp Hardware Reset (Active Low): The use of this lead at
LVTTL
LVTTL
LVTTL
Type
8mA
- Lead Descriptions -
transmit clock synthesizer.
The clock rate is programmable to be 19.44, 77.76 or 155.52
MHz. A 622.08 MHz clock can be provided when the Tx PLL
is bypassed. The frequency tolerance for this clock is ± 20
ppm. The maximum jitter on this clock should be confined to a
bandwidth of 5 kHz - 5 MHz and to the values shown below
depending on the selected frequency as indicated:
Receive Reference Clock: Optional Reference clock for the
receive clock and data recovery units. This clock is required
for line/loop-time applications, when REFTXCLK1 and
REFTXCLK2P/N are not present.
The clock rate is programmable to be either 19.44 or 77.76
MHz. The frequency tolerance for this clock is ± 100 ppm.
One Second Clock: Optional one second reference for per-
formance monitoring counters.
This is a 1.0 Hz ± 32 ppm clock input which is asynchronous
with other clock inputs/outputs, and has a minimum pulse
width of 2 77.76 MHz clock cycles = 25.72 ns (because syn-
chronized). If used, the one second counters are shadowed
after detection of the rising edge of this input.
Transmit Reference Frame Sync: Optional 8 kHz reference
frame sync pulse. If present, this input must be synchronous
to LINETXCLK and shall be at least 1 77.76 MHz clock cycle
wide = 12.86 ns
System Reference Frame Sync: 8 kHz reference frame
sync pulse. This output has a pulse width of 1 77.76 MHz
clock cycle (12.86 ns) and shall be synchronous to the
LINETXCLK when this last one is not divided down to 19.44
MHz
power-up is mandatory. Holding this lead for at least 50 ns
causes all the registers in the device to be reset.
Applied Reference
Clock Frequency
155.52
622.08
(MHz)
19.44
77.76
Name/Function
ps RMS
Maximum Reference Clock Jitter
40
40
40
40
PRELIMINARY TXC-06412B-MB, Ed. 2
OC-3
ps pp
280
280
280
280
PHAST-12P Device
ps RMS
8
8
8
8
DATA SHEET
OC-12
TXC-06412B
ps pp
June 2005
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