TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 177

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

1 7 7 o f 2 26
Offset
Offset
0x0000 3 - 0
0x0000
0x0090
0x0092
7 - 4
11 - 8
Bits
Bits
TimeslotIsConcatenated
Has_AU3
Reserved
RAM
Mode
Control
Table 20: POH Generator Path Configuration
Table 19: AUG-1 Mode Configuration
Name
Name
- Memory Maps and Bit Descriptions -
Init
Init
0xF Reserved.
0x0 Concatenation setting, one bit per AUG-1.
0x0 Selection between AU-3 and AU-4 mapping for independent AUG-1’s,
Each bit has following meaning (Least significant bit represents the first
AUG-1. Don’t care for line side in STM-1 mode):
The corresponding AUG-1 is either an independent AUG-1 or the first
AUG-1 of a larger concatenated structure when ‘0’ (e.g., AU4-4c). The
corresponding AUG-1 is part of a larger concatenated structure (but
not the first one) when ‘1’.
Note: The least significant bit must be ‘0’ (the first AUG-1 is always
master). This bit will be forced to ‘0’, no matter what has been written to
it.
one bit per AUG-1.
Each bit has following meaning (Least significant bit represents the first
AUG-1. For the line side: least significant bit represents the first AUG-
1 in STM-4 mode or the first line in STM-1 mode):
The corresponding AUG-1 contains an AU-4 when ‘0’, the
corresponding AUG-1 contains three AU-3’s when ‘1’.
Note the configuration is a don’t care for AUG-1’s which are part of a
larger concatenated structure. It is advisable to fill in the default value.
T_VCXPG_RAMBytes
Configuration of the POH RAM bytes.
T_VCXPG_Mode_record
Mode Configuration.
T_VCXPG_Control_record
Source selection for the POH bytes.
(T_AUG1_Mode_Config)
(T_VCXPG_VC_Config)
(See page
(See page
Description
(See page
Description
PRELIMINARY TXC-06412B-MB, Ed. 2
178.)
178.)
PHAST-12P Device
179.)
DATA SHEET
TXC-06412B
June 2005