TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 138

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
11.12 ATM CELL HANDLING
11.12.1 Egress Direction
11.12.1.1 Shared Settings for all ATM streams
11.12.1.2 Per ATM Stream Settings
The PHAST-12P performs the following ATM PHY layer functions, according to [ITU-T I.432]:
Cells are only passed to the ATM layer while processed in the SYNC state. Remark that the
DELTAth cell that triggers the transition to the SYNC state will further be processed as in the
SYNC state, this means filtering, descrambling and passing to ATM layer. The same applies
to the ALPHAth cell that triggers the transition to the HUNT state, this cell will be further
processed as in the HUNT state, i.e., no descrambling and no passing to the ATM layer.
Loss of Cell Delineation (LCD) signaling towards Tx path (through internal or external Ring
port). During LCD, the SDH/SONET POH Generator will insert E-RDI Payload in the G1 byte,
unless the insertion is disabled for that path.
Up to 12 ATM streams can be handled concurrently. On SDH/SONET, each ATM stream
corresponds to a VC-3/VC-4/VC-4-Xc/STS-1/STS-3c/STC-6c/STS-9c/STS-12c SPE. On the
UTOPIA interface, each ATM stream corresponds to a PHY.
• Egress: ATM cell demapping from SDH/SONET streams
• Ingress: ATM cell mapping into SDH/SONET streams
• Loss of Cell Delineation (LCD) integration time (0, 1, 2, 3 or 4 milliseconds)
• Enable/disable one second performance monitoring mechanism (shared with egress
• Number of free words which needs to be available before it is allowed to start writing a
• Enable/disable demapping (shared with egress PPP)
• Cell delineation
• Cell delineation including header error detection and correction
• HEC checking
• Filtering of idle cells, unassigned cells, user defined pattern cells, cells with
• Loss of Cell Delineation (LCD) detection and Tx RDI-P insertion
• Rx FIFO overflow detection
• Performance counters
• HEC checking, calculation and insertion
• Insertion of idle, unassigned and user defined pattern cells
• Performance counters
PPP)
new cell to the Rx FIFO (shared with egress PPP). For ATM cell handling it is mandatory
to set this value to 27.
• Threshold for leaving SYNC-state = ALPHA (1 . . . 15)
• Threshold for entering SYNC-state = DELTA (1 . . . 15)
• Enable/disable transition from Correction- to Detection-state while in SYNC: when
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High Order Pointer Tracking, Retiming and Pointer Generation
uncorrected HEC error
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1 3 8 o f 2 26