TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 13

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

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The PHAST
for ATM cell or PPP packet payload mappings. A single PHAST-12P can terminate four
individual STM-1/OC-3 lines or a single STM-4/OC-12 line. Each SDH/SONET terminator has
a line interface block that performs clock synthesis and clock recovery for four 155.52 Mbit/s
signals or a single 622.08 Mbit/s serial signal. It provides glueless 1+1, 1:1 and 1:n APS for
STM-1/OC-3 and STM-4/OC-12 applications using a 622.08 Mbit/s serial APS port interface.
The PHAST-12P performs RS (section) and MS (line) overhead processing, high order
pointer tracking and retiming, and high order path overhead processing and performance
monitoring. It contains a full non-blocking cross connect at the high order path level with
VC-3/STS-1 SPE granularity allowing path loopbacks, MS or line protection and UPSR and
SNC/P path protection. It can terminate ATM payloads from any of the above signals into a
16-bit UTOPIA Level 2 PHY interface. PPP payloads are terminated into a 16-bit wide
POS-PHY Level 2 interface.
Fully functional Device Driver software exists including comprehensive API’s, documentation
and sample application code which is made available on-line for registered users or through
TranSwitch Applications Engineering group. The sample applications represent different
modes of operation for the device with the proper procedures and sequencing of routines that
may contain multiple API’s and parameters to more easily implement these specific
applications.
The PHAST-12P device provides RS/section and MS/line overhead processing, high order
AU-3/AU-4/AU-4-Xc/STS-1/STS-3c/STC-6c/STS-9c/STS-12c pointer tracking and retiming,
and high order VC-3/VC-4/VC-4-Xc/STS-1/STS-3c/STS-6c/STS-9c/STS-12c SPE path
overhead processing and performance monitoring. It provides full non-blocking cross
connecting at the high order path level allowing path loopbacks, line/MSP protection and
UPSR and SNC/P path protection.
The device supports the following APS architectures:
1. STM-4/OC-12 mode: 1+1 or 1:1 APS using two devices connected via the APS port
2. STM-1/OC-3 mode: 1+1, 1:1 or 1:n (n<=3) APS using a single device without APS
3. STM-1/OC-3 mode: 1+1, 1:1 or 1:n (n<=7) APS using two devices connected via the
port
APS port
®
-12P is a highly integrated SDH/SONET overhead terminator device designed
PRELIMINARY TXC-06412B-MB, Ed. 2
PHAST-12P Device
O
VERVIEW
DATA SHEET
TXC-06412B
June 2005