TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 187

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

1 8 7 o f 2 26
Offset
0x0000
0x0200
0x0240
0x0280
12.11 TOH AND DCC PORT
Bits
TOH_Events_Mask
Common_Config
Line_Config
TOH_Events_Summary
Table 37: Receive TOH and DCC Port
Name
- Memory Maps and Bit Descriptions -
Init
All 0x1 rw
All 0x0 ro
rw
rw
Access
Array (36) of nine_bits
Offset between two elements = 0x2.
Array index indicates the summary of nine TOH byte
events.
Masks for the corresponding events. Refer to
TOH_Events_LatchForInt descriptions for the layout of
the bits.
T_RXTDP_Common_Config
General configuration.
Array (4) of T_RXTDP_Line_Config
Offset between two elements = 0x2.
Array index indicates the line (= line number - 1).
DCC port configuration.
Array (4) of nine_bits
Offset between two elements = 0x2.
Array index indicates the summary of nine
TOH_Events_LatchedForInt bits.
Each bit corresponds to the summary of one entry in
TOH_Events_LatchForInt. Each entry of this array
corresponds to the summaries of all TOH byte events for
the bytes with the same interleave depth (STM-4 mode),
or with the same line number (STM-1 mode).
The array index and the bit position can be calculated as
follows:
Array index = c-1
The correlation between bit position and
TOH_Events_LatchForInt entry is as follows:
A bit p corresponds to the summary of TOH Events entry
(px4) + c.
where
See also [ITU-T G.707/Y.1322] for the TOH bytes
locations.
(T_RX_TOH_DCC_PORT)
• a = row number (1 to 9),
• b = multi-column number (1 to 9),
• c, for STM-4 mode = depth of the interleave within
• c, for STM-1 mode = line number (1-4).
• p = bit position (0 to 8, least significant bit is 0)
the multi-column (1-4),
PRELIMINARY TXC-06412B-MB, Ed. 2
Description
PHAST-12P Device
(See page
(See page
DATA SHEET
189.)
TXC-06412B
June 2005
189.)