TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 6

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
12.0 Memory Maps and Bit Descriptions........................................................................................... 167
Package Information ........................................................................................................................... 220
Application Examples .......................................................................................................................... 221
Ordering Information ........................................................................................................................... 222
Related Products ................................................................................................................................. 222
Standards Documentation Sources..................................................................................................... 223
Please note that TranSwitch provides documentation for all of its products. Current editions of many documents are
available from the Products page of the TranSwitch Web site at www.transwitch.com. Customers who are using a
TranSwitch Product, or planning to do so, must register with the TranSwitch Marketing Department to receive relevant
updated and supplemental documentation as it is issued. They must also contact the Applications Engineering
Department to ensure that they are provided with the latest available information about the product, especially before
undertaking development of new designs incorporating the product.
11.19 Trail Trace Identifier Process............................................................................................. 151
11.20 Performance Counters ...................................................................................................... 152
11.21 Defects and Interrupts ....................................................................................................... 155
11.22 Alarm Interrupt Tree .......................................................................................................... 156
11.23 Boundary Scan .................................................................................................................. 165
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
12.10 TOH Generator.................................................................................................................. 185
12.11 TOH and DCC Port............................................................................................................ 187
12.12 High Order Pointer Tracker and Retimer........................................................................... 189
12.13 POS/ATM Demapper......................................................................................................... 192
12.14 POS/ATM Mapper ............................................................................................................. 196
12.15 Pointer Generator .............................................................................................................. 200
12.16 Clock Recovery/Clock Synthesis/Serdes .......................................................................... 201
12.17 Receive APS Port.............................................................................................................. 207
12.18 Cross Connect................................................................................................................... 209
12.19 Egress UTOPIA/POS-PHY Level 2 Interface .................................................................... 210
12.20 High Order Path Ring Port/Alarm Interface ....................................................................... 212
12.21 JTAG Master ..................................................................................................................... 213
12.22 POH Monitor...................................................................................................................... 214
11.19.1
11.19.2
11.19.3
11.20.1
11.20.2
11.21.1
11.21.2
11.21.3
11.21.4
11.23.1
11.23.2
11.23.3
11.23.4
Overview............................................................................................................................ 167
Global Control.................................................................................................................... 168
Line Ring Port/Alarm Interface .......................................................................................... 170
Reset Generator ................................................................................................................ 170
Interrupt ............................................................................................................................. 171
Transmit APS Port............................................................................................................. 173
Ingress UTOPIA/POS-PHY Level 2 Interface.................................................................... 174
POH Generator.................................................................................................................. 176
TOH Monitor ...................................................................................................................... 180
TTI Formats ............................................................................................................ 151
TTI Mismatch Process ............................................................................................ 152
TTI Report Process................................................................................................. 152
SDH/SONET Related Performance Counters ........................................................ 152
ATM/PPP Related Performance Counters ............................................................. 153
Unlatched Defects (Correlated) .............................................................................. 155
Latched Defects...................................................................................................... 155
Defects Mask .......................................................................................................... 155
Interrupts................................................................................................................. 155
Introduction ............................................................................................................. 165
Boundary Scan Operation ...................................................................................... 165
Boundary Scan Reset............................................................................................. 166
Boundary Scan Chain............................................................................................. 166
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