TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 147

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

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11.15.1.1 Shared Settings for all POS-PHY Ports
11.15.1.2 Per POS-PHY Port Settings
11.15.1.3 Per CLAV Setting
11.15.1.4 Per POS-PHY Port Status & Alarms
The maximum clock frequency is 50 MHz and the data and control signals are transferred on
the rising edge of this clock.
All incoming packets must be larger than 6 bytes.
• Enable/disable entire interface (shared with Tx UTOPIA)
• PHY Mode: single-PHY or multi-PHY (shared with Tx UTOPIA)
• Following two Status indication Modes are possible (mix is not supported - shared with Tx
• Odd or even parity (shared with Tx UTOPIA)
• Parity over data or data and control signals (shared with Tx UTOPIA)
• FIFO threshold high: the number of free words which has to be available in the Tx FIFO
• FIFO threshold low: if there are equal or less free words available in the Tx FIFO, the
• Threshold: if there are equal or less free words available in the Tx FIFO, the related STPA
• Enable/disable PHY port (shared with Tx UTOPIA)
• PHY Port address (shared with Tx UTOPIA)
• Timeslot for direct status (shared with Tx UTOPIA)
• SOP-EOP error
• Parity error (shared with Tx UTOPIA)
• Overflow error (shared with Tx UTOPIA)
• Output selected PHY packet available PPTXSTPA
• Output polled PHY packet available PPUTPTPACLAV(3-0)
UTOPIA):
• Direct status: at most 4 DTPA’s are used, at most 4 PHY’s are possible
• Multiplexed status with full addressing: 1 PTPA (PTPA0) signal is used, at most 31
to trigger the assertion of the related PTPA signal.
related PTPA signal is deasserted
signal is deasserted
- High Order Pointer Tracking, Retiming and Pointer Generation -
PHY’s are possible
PRELIMINARY TXC-06412B-MB, Ed. 2
PHAST-12P Device
DATA SHEET
TXC-06412B
June 2005