TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 205

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

2 0 5 o f 2 26
0x000C
0x000A
0x000E
Offset
0x0000
0x0002
0x0004
0x0006
0x0008
Offset
0x0000
0x0002
0x0004
9-0
0
13-0
14-0
0
4 - 0
15 - 0
15 - 0
0
2 - 0
0
Bits
Bits
Table 68: Setup of Clock Recovery/Clock Synthesis/SerDes
TxPowerDown
LineRate
RxPowerDown1
RxPowerDown2
ToplevelPowerDown
OC3NotOC12
PRBSBitErrorCounter
IndirectAccessData
TimingMode
LineTimingChannel
TxRefSelect
Name
Name
- Memory Maps and Bit Descriptions -
Table 69: PLL Control
Init
0x0
0x0
0x0
0x3FFF
0x7FFF
0x3FF
Init
0x1F
External/Line timing mode selection for the transmit PLL.
External timing mode is selected when 0x0, TxRefSelect selects the exter-
nal source.
Line-Timing mode is selected when 0x1, LineTimingChannel selects the line
timing channel.
Range 0 to 4
Line timing mode channel selection.
This field is only used when TimingMode is ‘1’. The value indicates the line.
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•
•
•
•
Transmit reference clock external source selection for the PLL in the trans-
mit section.
This field is only valid when TimingMode is ‘0’.
•
•
0x0
0x1
0x0
0x0
0x0: Line 1
0x1: Line 2
0x2: Line 3
0x3: Line 4
0x4: APS
0x0: REFTXCLK1 is used as reference clock
0x1: REFTXClK2 is used as reference clock
Power down for the SerDes transmit section.
Must be set to 0x0 at power-up.
Indicates the line rate for the selected line when line timing is used.
Line rate is 155.52 Mbit/s when 0x0, 622.08 Mbit/s when 0x1.
Note: This setting is only applicable for the line selected by LineTim-
ingChannel when TimingMode is 0x1.
Power down for the SerDes receive section.
Must be set to 0x0 at power-up.
Power down for the SerDes receive section.
Must be set to 0x0 at power-up.
Power down for the toplevel SerDes bias module.
Must be set to 0x0 at power-up.
Line Rate Configuration
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•
Bit Error counter of the PRBS analyzer at the cross connect.
This (read-only) counter is clear-on-read.
Indirect Access Data register. When a write is done to this register,
the field specified by the IndirectAccessMode will be configured.
Following values need to be set when initializing the CDR/CS:
•
•
0x0E: STM-4 Mode
0x0F: STM-1 Mode
All others: Reserved
0x0017 to IndirectAccessMode Mode0
0x5000 to IndirectAccessMode Mode1
(T_PLL_Control)
Description
Description
PRELIMINARY TXC-06412B-MB, Ed. 2
(T_CDR_CS_Setup)
PHAST-12P Device
DATA SHEET
TXC-06412B
June 2005