TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 19

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

1 9 o f 2 2 6
1.11 POS-PHY LEVEL 2 INTERFACE (PHY LAYER)
1.12 MICROPROCESSOR INTERFACE
1.13 TESTING
1.14 DEVICE DRIVER
• Odd/even parity over data or data and control signals
• Detection of unexpected or missing SOC
• Pins shared with UTOPIA level 2 interface
• 16 bit data bus width
• Maximum clock speed 50 MHz
• Packet level handshaking for up to twelve high order path packet streams
• Single-PHY or multi-PHY mode
• Status indication modes
• Odd/even parity over data or data and control signals
• Detection of missing SOP and missing EOP
• Bidirectional 16-bit wide Data bus (allowing 16-bit word accesses only)
• 14-bit wide Address bus
• The following microprocessor interface modes are supported:
• Interrupt request lead
• Interrupt mask bits for controlling generation of hardware interrupt requests
• Line loopbacks
• High order path loopbacks via the cross-connect
• Boundary scan
• Device configuration
• Fault monitoring
• Performance monitoring
• Direct status indication, see [UTOPIA Level 2] section 4.3: at most 4 CLAV’s are used,
• Multiplexed status polling with full address, see [UTOPIA Level 2] section 4.2: 1 CLAV
• Multiplexed status polling with group address, see [UTOPIA Level 2] section 4.4: 4
• Direct status indication: at most 4 DTPA’s are used, at most 4 PHY’s are possible
• Multiplexed status polling with full address: 1 PTPA signal (PTPA0) is used, at most 31
• Generic Motorola mode
• Generic Intel mode (with separate address/data bus)
• MPC860 mode
• MPC8260 Local Bus mode
at most 4 PHY’s are possible
signal (CLAV0) is used, at most 31 PHY’s are possible
CLAV signal are used, at most 31 PHY’s are possible
PHYs are possible
- Features -
PRELIMINARY TXC-06412B-MB, Ed. 2
PHAST-12P Device
DATA SHEET
TXC-06412B
June 2005