TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 18

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
1.9 PPP PACKET HANDLING
1.10 UTOPIA LEVEL 2 INTERFACE (PHY LAYER)
• Ingress: ATM cell mapping into SDH/SONET streams
• Egress: PPP packet demapping from SDH/SONET streams
• Ingress: PPP packet mapping into SDH/SONET streams
• Pins shared with POS-PHY level 2 interface
• 16 bit data bus width, or 8 bit data bus with reduced bandwidth
• Maximum clock speed 50 MHz
• Cell level handshaking for up to twelve high order path cell streams
• Single-PHY or multi-PHY mode
• Status indication modes
• Filtering of idle cells, unassigned cells, user defined pattern cells, cells with
• Detection of loss of cell delineation and RDI-P insertion
• Detection of Rx FIFO overflow
• Performance counters
• HEC checking, calculation and insertion
• Insertion of idle, unassigned and user defined pattern cells
• Performance counters
• Descrambling
• Address/control fields checking and stripping
• HDLC framing and byte destuffing, including escape character discarding
• FCS checking and stripping
• 32/16 bit FCS
• Detection of Rx FIFO overflow
• Discarding of too short and too long frames
• Discarding of frames with abort sequence
• Performance counters
• Optional Transparent demapping
• Address/control fields insertion
• FCS insertion
• 32/16 bit FCS
• HDLC flag insertion and byte stuffing, including escape character insertion
• Optional multiple flag insertion
• Scrambling
• Detection of Tx FIFO underflow
• Detection of errored packets and insertion of abort sequence
• Performance counters
• Optional Transparent mapping
uncorrected HEC error
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Features
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