TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 93

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

9 3 o f 2 2 6
As the PHAST-12P is a PHY-layer device, it gets both Receive and Transmit UTOPIA/POS-
PHY clocks as inputs. These clocks are generated by the ATM/Link layer device. Clock
boundary crossings from/to the System Clock are done in Rx and Tx Cell/Packet FIFOs.
The System Clock is available on an output lead: LINETXCLK, optionally divided down to
19.44 MHz.
The PHAST-12P’s internal Clock Recovery units, operating on the four SDH/SONET Receive
Line interfaces and the Receive APS Port generate five recovered clocks: one for each
channel.
Internally, these units require a high-speed Receive Clock, which is synthesized using a
selectable Rx timebase.
The recovered data from the four SDH/SONET Receive Lines and from the Receive APS
Port is retimed to the System Clock, before entering the Cross-Connect.
Divided-down versions of each recovered clock are available on output leads: LINERXCLK1
(19.44 or 77.76 MHz), LINERXCLK2 (19.44 MHz), LINERXCLK3 (19.44 MHz), LINERXCLK4
(19.44 MHz), and APSRXCLK (19.44 or 77.76 MHz).
The Tx timebase can be selected using control bits:
The frequency of REFTXCLOCK1 is selectable:
The frequency of REFTXCLOCK2P/N is selectable:
The Rx timebase can be selected using control bits:
• Either one of the two external Transmit Clock sources: REFTXCLK1 or REFTXCLK2P/N
• The recovered 622.08 MHz Receive APS Port clock (External Timing) (control field:
• The recovered 622.08 MHz clock in STM-4/OC-12 application (Line/Loop - Timing) (con-
• Any of the four recovered 155.52 MHz clocks in STM-1/OC-3 application (Line/Loop -
• 19.44 MHz
• 77.76 MHz
• 19.44 MHz
• 77.76 MHz
• 155.52 MHz
• 622.08 MHz (bypass mode)
(External Timing) (control field TxRefSelect, see
Descriptions)
LineTimingChannel and TimingMode, see
Descriptions)
trol field: LineTimingChannel and TimingMode, see
Bit
Timing) (control field: LineTimingChannel and TimingMode, see
ory Maps and Bit
Descriptions)
Descriptions)
- Operation -
Table 69
Table 69
Table 69
PRELIMINARY TXC-06412B-MB, Ed. 2
of the
of the
of the
PHAST-12P Device
Memory Maps and Bit
Memory Maps and Bit
Table 69
Memory Maps and
DATA SHEET
TXC-06412B
of the
June 2005
Mem-