TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 213

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

2 1 3 o f 2 26
Offset
0x000C 0
0x001A 7 - 0
0x001C 7 - 0
0x001E 7 - 0
0x002A 7 - 0
0x002C 7 - 0
0x002E 7 - 0
0x003A 0
0x003C 0
0x003E 0
0x0000 0
0x0004 1 - 0
0x0008 0
0x0010 7 - 0
0x0012 5 - 0
0x0014 7 - 0
0x0016 7 - 0
0x0018 7 - 0
0x0020 7 - 0
0x0022 7 - 0
0x0024 7 - 0
0x0026 7 - 0
0x0028 7 - 0
0x0030 7 - 0
0x0032 0
0x0034 1 - 0
0x0036 0
0x0038 0
12.21 JTAG MASTER
Bits
Bit_wise_control
TCK_bit
TDO_bit
TCK_DIVIDER
TDI_Fifo_B3
TMS_Fifo_B0
TDO_Fifo_B1
TDO_Fifo_B3
Start
JM_TRSTN
TDI_LoopBack
TMS_LoopBack
TRSTN_Sample
uProcessor_CNTRL
TDI_TMS_bit
Counter
TDI_Fifo_B0
TDI_Fifo_B1
TDI_Fifo_B2
TDI_Fifo_B4
TMS_Fifo_B1
TMS_Fifo_B2
TMS_Fifo_B3
TMS_Fifo_B4
TDO_Fifo_B0
TDO_Fifo_B2
TDO_Fifo_B4
Done
Name
- Memory Maps and Bit Descriptions -
Table 87: JTAG Master
Init
0x0 rw
0x0 rw
0x0 rw
0x0 ro
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 rw
0x0 ro
0x0 ro
0x0 ro
0x0 ro
0x0 ro
0x0 rw
0x0 ro
0x0 rw
0x0 rw
0x0 rw
0x0 ro
0x1 rw
Access
(T_JTAG_MASTER)
This bit selects if direct microprocessor control bits will be
used, instead of the FIFO’s.
The microprocessor driven TDI and TMS bit values (bit 0 =
TMS, bit 1 = TDI).
The microprocessor driven TCK clock bit value.
The microprocessor read TDO bit value.
A clock divider number to create an appropriate 10 MHz
TCK clock using the current system clock.
6-bit shift count register.
FIFO containing TDI data to send to TAP (byte 0).
FIFO containing TDI data to send to TAP (byte 1).
FIFO containing TDI data to send to TAP (byte 2).
FIFO containing TDI data to send to TAP (byte 3).
FIFO containing TDI data to send to TAP (byte 4).
FIFO containing TMS data to send to TAP (byte 0).
FIFO containing TMS data to send to TAP (byte 1).
FIFO containing TMS data to send to TAP (byte 2).
FIFO containing TMS data to send to TAP (byte 3).
FIFO containing TMS data to send to TAP (byte 4).
FIFO containing TDO data received from the TAP (byte 0).
FIFO containing TDO data received from the TAP (byte 1).
FIFO containing TDO data received from the TAP (byte 2).
FIFO containing TDO data received from the TAP (byte 3).
FIFO containing TDO data received from the TAP (byte 4).
Start bit. Is set to trigger a transfer between microprocessor
& TAP. This bit clears the Done and Error bits.
When the transfer is completed, these bits are set:
The value of TRSTN driven by the microprocessor
interface.
This bit loops back the TDI FIFO output, back into the TDO
FIFO Input (Used for test).
This bit loops back the TMS FIFO output, back into the TDO
FIFO Input (Used for test).
This bit samples what the microprocessor interface is
driving into the TAP.
This bit switches the TAP control over to the
microprocessor.
• bit 0 = ‘Done’
• bit 1 = ‘Error’
PRELIMINARY TXC-06412B-MB, Ed. 2
Description
PHAST-12P Device
DATA SHEET
TXC-06412B
June 2005